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@@ -5,13 +5,32 @@
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#define HF_REG_BASE 0x00
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#define HF_REG_DMA 0x04
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+#define HF_REG_PACKET_LENGTH 0x0C
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#define HF_REG_NUM_PACKETS 0x10
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+#define HF_REG_INT_REG_VERSION 0x18
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+#define HF_REG_PERF_COUNTER_4ns 0x1C
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+#define HF_REG_PERF_COUNTER_FEEDBACK_1 0x20
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+#define HF_REG_PERF_COUNTER_FEEDBACK_2 0x24
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#define HF_REG_PERF_COUNTER 0x28
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-#define HF_REG_PACKET_LENGTH 0x0C
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+#define HF_REG_MULTI_2_EMPTY_COUNTER 0x30
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+#define HF_REG_MULTI_2_FEEDBACK1 0x34
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+#define HF_REG_MULTI_2_FEEDBACK2 0x38
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+#define HF_REG_RESULT_LATENCY_MASTER 0x3C
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+#define HF_REG_NUM_DESC_INSIDE 0x40
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#define HF_REG_DESCRIPTOR_ADDRESS 0x50
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#define HF_REG_UPDATE_ADDRESS 0x58
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#define HF_REG_UPDATE_THRESHOLD 0x60
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#define HF_REG_TIMER_THRESHOLD 0x64
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+#define HF_REG_DESCRIPTOR_AMD_SIGNAL 0x70
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+
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+#define HF_REG_CONF_DMA_TX_ENGINE 0x100
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+#define HF_REG_LATENCY_NUM_MEAS 0x104
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+#define HF_REG_LATENCY_REPEAT_MASK 0x108
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+#define HF_REG_LATENCY_TIMEOUT 0x10C
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+
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+#define HF_REG_DESC_LATENCY_DATA 0x110
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+#define HF_REG_DESC_LATENCY_RESULTS 0x118
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+
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/* internal register masks and values */
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@@ -28,17 +47,23 @@
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#define HF_REG_DCG 0x9000
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#define HF_REG_DCG_FIXED_PATTERN 0x9004
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#define HF_REG_DCG_FIXED_PATTERN_1ST 0x9008
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+#define HF_REG_DCG_UPPER_LIMIT 0x900C
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#define HF_REG_VERSION 0x9030
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#define HF_REG_CONTROL 0x9040
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-#define HF_REG_LATENCY 0x9044
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#define HF_REG_INTERCONNECT 0x9048
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+#define HF_REG_DDR_START_ADDR 0x9050
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+#define HF_REG_DDR_UPPER_ADDR 0x9054
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+#define HF_REG_DDR_RD_ADDR 0x9070
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+#define HF_REG_DDR_WR_ADDR 0x9074
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#define HF_REG_DFG_NUM_ROWS 0x9168
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#define HF_REG_DFG_NUM_FRAMES 0x9170
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+#define HF_REG_DEBUG_RC_RESET 0x92e4
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#define HF_REG_DEBUG_REQUESTER_RESET 0x9344
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#define HF_REG_DEBUG_COMPLETER_RESET 0x93A4
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/* user register masks and values */
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+#define HF_DCG_STOP 0x0
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#define HF_DCG_START 0x00000001
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#define HF_DCG_RESET 0x00000010
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#define HF_DCG_ENABLE_FIXED_PATTERN 0x00000100
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@@ -53,9 +78,11 @@
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#define HF_CONTROL_SOURCE_DFG 0x00020000
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#define HF_CONTROL_SOURCE_DCG_NO_DDR 0x00030000
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-#define HF_INTERCONNECT_MASTER_DMA 0x2
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-#define HF_INTERCONNECT_SLAVE_DMA 0x1
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-#define HF_INTERCONNECT_DDR_TO_DMA 0x60
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-#define HF_INTERCONNECT_DDR_FROM_64 0x200
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+#define HF_INTERCONNECT_MASTER_DMA 0x2
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+#define HF_INTERCONNECT_SLAVE_DMA 0x1
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+#define HF_INTERCONNECT_DDR_TO_DMA 0x60
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+#define HF_INTERCONNECT_DDR_FROM_64 0x200
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+#define HF_INTERCONNECT_DDR_FROM_CNT 0x300
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+#define HF_INTERCONNECT_DDR_FROM_RX_MASTER 0x500
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#endif
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