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@@ -31,6 +31,7 @@
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#define HF_REG_VERSION 0x9020
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#define HF_REG_CONTROL 0x9040
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#define HF_REG_LATENCY 0x9044
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+#define HF_REG_INTERCONNECT 0x9048
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#define HF_REG_DFG_NUM_ROWS 0x9168
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#define HF_REG_DFG_NUM_FRAMES 0x9170
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#define HF_REG_DEBUG_REQUESTER_RESET 0x9344
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@@ -52,4 +53,9 @@
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#define HF_CONTROL_SOURCE_DFG 0x00020000
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#define HF_CONTROL_SOURCE_DCG_NO_DDR 0x00030000
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+#define HF_INTERCONNECT_MASTER_DMA 0x2
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+#define HF_INTERCONNECT_SLAVE_DMA 0x1
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+#define HF_INTERCONNECT_DDR_TO_DMA 0x60
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+#define HF_INTERCONNECT_DDR_FROM_64 0x200
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+
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#endif
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