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@@ -97,6 +97,7 @@ pcilib_context_t *ipecamera_init(pcilib_t *pcilib) {
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FIND_REG(status_reg, "fpga", "status");
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FIND_REG(control_reg, "fpga", "control");
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+ FIND_REG(status2_reg, "fpga", "status2");
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FIND_REG(status3_reg, "fpga", "status3");
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FIND_REG(n_lines_reg, "cmosis", "cmosis_number_lines");
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@@ -304,8 +305,9 @@ int ipecamera_start(pcilib_context_t *vctx, pcilib_event_t event_mask, pcilib_ev
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if (value&0x1000) ctx->fr_mode = 1;
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else {
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ctx->fr_mode = 0;
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- CHECK_STATUS_REG();
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- if (err) return err;
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+
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+// CHECK_STATUS_REG();
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+// if (err) return err;
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}
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ctx->event_id = 0;
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@@ -659,12 +661,28 @@ int ipecamera_trigger(pcilib_context_t *vctx, pcilib_event_t event, size_t trigg
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return PCILIB_ERROR_BUSY;
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}
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*/
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-/*
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- do {
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- usleep(10);
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- GET_REG(status3_reg, value);
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- } while (value&0x20000000);
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-*/
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+
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+ GET_REG(status2_reg, value);
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+ if (value&0x40000000) {
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+// printf("%x\n", value);
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+// GET_REG(status3_reg, value);
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+// printf("3: %x\n", value);
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+// GET_REG(status_reg, value);
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+// printf("1: %x\n", value);
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+
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+#ifdef IPECAMERA_TRIGGER_WAIT_IDLE
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+ if (IPECAMERA_TRIGGER_WAIT_IDLE) {
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+ struct timeval deadline;
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+ pcilib_calc_deadline(&deadline, IPECAMERA_TRIGGER_WAIT_IDLE);
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+ do {
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+ usleep(IPECAMERA_READ_STATUS_DELAY);
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+ GET_REG(status2_reg, value);
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+ } while ((value&0x40000000)&&(pcilib_calc_time_to_deadline(&deadline) > 0));
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+ }
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+ if (value&0x40000000)
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+#endif /* IPECAMERA_TRIGGER_WAIT_IDLE */
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+ return PCILIB_ERROR_BUSY;
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+ }
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GET_REG(control_reg, value);
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SET_REG(control_reg, value|IPECAMERA_FRAME_REQUEST);
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@@ -672,7 +690,7 @@ int ipecamera_trigger(pcilib_context_t *vctx, pcilib_event_t event, size_t trigg
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//CHECK_REG(status_reg, IPECAMERA_EXPECTED_STATUS);
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SET_REG(control_reg, value);
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-
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+ // We need to compute it differently, on top of that add exposure time and the time FPGA takes to read frame from CMOSIS
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pcilib_calc_deadline(&ctx->next_trigger, IPECAMERA_NEXT_FRAME_DELAY);
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return 0;
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