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@@ -26,13 +26,10 @@ pcilib_register_bank_description_t ipecamera_register_banks[] = {
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{ PCILIB_REGISTER_DMABANK0, PCILIB_BAR0, 128, PCILIB_DEFAULT_PROTOCOL, DMA_NWL_OFFSET, DMA_NWL_OFFSET, PCILIB_LITTLE_ENDIAN, 32, PCILIB_LITTLE_ENDIAN, "%lx", "dma", "NorthWest Logick DMA Engine" },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL }
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};
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-
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-pcilib_register_description_t dma_nwl_registers[] = {
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- {0, 0, 32, 0, PCILIB_REGISTER_R , PCILIB_REGISTER_DMABANK, "dma_capabilities", ""},
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- {1, 0, 32, 0, PCILIB_REGISTER_RW, PCILIB_REGISTER_DMABANK, "dma_control", ""},
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-};
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*/
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+
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+
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typedef struct {
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pcilib_dma_engine_description_t desc;
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char *base_addr;
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@@ -71,6 +68,7 @@ static int nwl_read_engine_config(nwl_dma_t *ctx, pcilib_nwl_engine_description_
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if ((val & DMA_ENG_PRESENT_MASK) == 0) return PCILIB_ERROR_NOTAVAILABLE;
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info->desc.addr = (val & DMA_ENG_NUMBER) >> DMA_ENG_NUMBER_SHIFT;
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+ if ((info->desc.addr > PCILIB_MAX_DMA_ENGINES)||(info->desc.addr < 0)) return PCILIB_ERROR_INVALID_DATA;
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switch (val & DMA_ENG_DIRECTION_MASK) {
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case DMA_ENG_C2S:
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