cli.c 76 KB

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  1. #define _POSIX_C_SOURCE 200112L
  2. #define _BSD_SOURCE
  3. #include <stdio.h>
  4. #include <stdlib.h>
  5. #include <string.h>
  6. #include <strings.h>
  7. #include <stdint.h>
  8. #include <stdarg.h>
  9. #include <fcntl.h>
  10. #include <unistd.h>
  11. #include <sys/time.h>
  12. #include <sys/ioctl.h>
  13. #include <sys/mman.h>
  14. #include <errno.h>
  15. #include <alloca.h>
  16. #include <arpa/inet.h>
  17. #include <sys/types.h>
  18. #include <dirent.h>
  19. #include <pthread.h>
  20. #include <getopt.h>
  21. #include "pcitool/sysinfo.h"
  22. //#include "pci.h"
  23. #include "tools.h"
  24. #include "kernel.h"
  25. #include "error.h"
  26. /* defines */
  27. #define MAX_KBUF 14
  28. //#define BIGBUFSIZE (512*1024*1024)
  29. #define BIGBUFSIZE (1024*1024)
  30. #define DEFAULT_FPGA_DEVICE "/dev/fpga0"
  31. #define LINE_WIDTH 80
  32. #define SEPARATOR_WIDTH 2
  33. #define BLOCK_SEPARATOR_WIDTH 2
  34. #define BLOCK_SIZE 8
  35. #define BENCHMARK_ITERATIONS 128
  36. #define isnumber pcilib_isnumber
  37. #define isxnumber pcilib_isxnumber
  38. #define isnumber_n pcilib_isnumber_n
  39. #define isxnumber_n pcilib_isxnumber_n
  40. typedef uint8_t access_t;
  41. typedef enum {
  42. GRAB_MODE_GRAB = 1,
  43. GRAB_MODE_TRIGGER = 2
  44. } GRAB_MODE;
  45. typedef enum {
  46. MODE_INVALID,
  47. MODE_INFO,
  48. MODE_LIST,
  49. MODE_BENCHMARK,
  50. MODE_READ,
  51. MODE_READ_REGISTER,
  52. MODE_WRITE,
  53. MODE_WRITE_REGISTER,
  54. MODE_RESET,
  55. MODE_GRAB,
  56. MODE_START_DMA,
  57. MODE_STOP_DMA,
  58. MODE_LIST_DMA,
  59. MODE_LIST_DMA_BUFFERS,
  60. MODE_READ_DMA_BUFFER,
  61. MODE_WAIT_IRQ,
  62. MODE_LIST_KMEM,
  63. MODE_READ_KMEM,
  64. MODE_FREE_KMEM
  65. } MODE;
  66. typedef enum {
  67. ACCESS_BAR,
  68. ACCESS_DMA,
  69. ACCESS_FIFO
  70. } ACCESS_MODE;
  71. typedef enum {
  72. FLAG_MULTIPACKET = 1,
  73. FLAG_WAIT = 2
  74. } FLAGS;
  75. typedef enum {
  76. FORMAT_RAW,
  77. FORMAT_HEADER,
  78. FORMAT_RINGFS
  79. } FORMAT;
  80. typedef enum {
  81. PARTITION_UNKNOWN,
  82. PARTITION_RAW,
  83. PARTITION_EXT4,
  84. PARTITION_NULL
  85. } PARTITION;
  86. typedef enum {
  87. OPT_DEVICE = 'd',
  88. OPT_MODEL = 'm',
  89. OPT_BAR = 'b',
  90. OPT_ACCESS = 'a',
  91. OPT_ENDIANESS = 'e',
  92. OPT_SIZE = 's',
  93. OPT_OUTPUT = 'o',
  94. OPT_TIMEOUT = 't',
  95. OPT_INFO = 'i',
  96. OPT_LIST = 'l',
  97. OPT_READ = 'r',
  98. OPT_WRITE = 'w',
  99. OPT_GRAB = 'g',
  100. OPT_QUIETE = 'q',
  101. OPT_HELP = 'h',
  102. OPT_RESET = 128,
  103. OPT_BENCHMARK,
  104. OPT_TRIGGER,
  105. OPT_DATA_TYPE,
  106. OPT_EVENT,
  107. OPT_TRIGGER_RATE,
  108. OPT_TRIGGER_TIME,
  109. OPT_RUN_TIME,
  110. OPT_FORMAT,
  111. OPT_BUFFER,
  112. OPT_LIST_DMA,
  113. OPT_LIST_DMA_BUFFERS,
  114. OPT_READ_DMA_BUFFER,
  115. OPT_START_DMA,
  116. OPT_STOP_DMA,
  117. OPT_WAIT_IRQ,
  118. OPT_ITERATIONS,
  119. OPT_LIST_KMEM,
  120. OPT_FREE_KMEM,
  121. OPT_READ_KMEM,
  122. OPT_FORCE,
  123. OPT_WAIT,
  124. OPT_MULTIPACKET
  125. } OPTIONS;
  126. static struct option long_options[] = {
  127. {"device", required_argument, 0, OPT_DEVICE },
  128. {"model", required_argument, 0, OPT_MODEL },
  129. {"bar", required_argument, 0, OPT_BAR },
  130. {"access", required_argument, 0, OPT_ACCESS },
  131. {"endianess", required_argument, 0, OPT_ENDIANESS },
  132. {"size", required_argument, 0, OPT_SIZE },
  133. {"output", required_argument, 0, OPT_OUTPUT },
  134. {"timeout", required_argument, 0, OPT_TIMEOUT },
  135. {"iterations", required_argument, 0, OPT_ITERATIONS },
  136. {"info", no_argument, 0, OPT_INFO },
  137. {"list", no_argument, 0, OPT_LIST },
  138. {"reset", no_argument, 0, OPT_RESET },
  139. {"benchmark", optional_argument, 0, OPT_BENCHMARK },
  140. {"read", optional_argument, 0, OPT_READ },
  141. {"write", optional_argument, 0, OPT_WRITE },
  142. {"grab", optional_argument, 0, OPT_GRAB },
  143. {"trigger", optional_argument, 0, OPT_TRIGGER },
  144. {"data", required_argument, 0, OPT_DATA_TYPE },
  145. {"event", required_argument, 0, OPT_EVENT },
  146. {"run-time", required_argument, 0, OPT_RUN_TIME },
  147. {"trigger-rate", required_argument, 0, OPT_TRIGGER_RATE },
  148. {"trigger-time", required_argument, 0, OPT_TRIGGER_TIME },
  149. {"format", required_argument, 0, OPT_FORMAT },
  150. {"buffer", optional_argument, 0, OPT_BUFFER },
  151. {"start-dma", required_argument, 0, OPT_START_DMA },
  152. {"stop-dma", optional_argument, 0, OPT_STOP_DMA },
  153. {"list-dma-engines", no_argument, 0, OPT_LIST_DMA },
  154. {"list-dma-buffers", required_argument, 0, OPT_LIST_DMA_BUFFERS },
  155. {"read-dma-buffer", required_argument, 0, OPT_READ_DMA_BUFFER },
  156. {"wait-irq", optional_argument, 0, OPT_WAIT_IRQ },
  157. {"list-kernel-memory", no_argument, 0, OPT_LIST_KMEM },
  158. {"read-kernel-memory", required_argument, 0, OPT_READ_KMEM },
  159. {"free-kernel-memory", required_argument, 0, OPT_FREE_KMEM },
  160. {"quiete", no_argument, 0, OPT_QUIETE },
  161. {"force", no_argument, 0, OPT_FORCE },
  162. {"multipacket", no_argument, 0, OPT_MULTIPACKET },
  163. {"wait", no_argument, 0, OPT_WAIT },
  164. {"help", no_argument, 0, OPT_HELP },
  165. { 0, 0, 0, 0 }
  166. };
  167. void Usage(int argc, char *argv[], const char *format, ...) {
  168. if (format) {
  169. va_list ap;
  170. va_start(ap, format);
  171. printf("Error %i: ", errno);
  172. vprintf(format, ap);
  173. printf("\n");
  174. va_end(ap);
  175. printf("\n");
  176. }
  177. printf(
  178. "Usage:\n"
  179. " %s <mode> [options] [hex data]\n"
  180. " Modes:\n"
  181. " -i - Device Info\n"
  182. " -l[l] - List (detailed) Data Banks & Registers\n"
  183. " -r <addr|reg|dmaX> - Read Data/Register\n"
  184. " -w <addr|reg|dmaX> - Write Data/Register\n"
  185. " --benchmark <barX|dmaX> - Performance Evaluation\n"
  186. " --reset - Reset board\n"
  187. " --help - Help message\n"
  188. "\n"
  189. " Event Modes:\n"
  190. " --trigger [event] - Trigger Events\n"
  191. " -g [event] - Grab Events\n"
  192. "\n"
  193. " DMA Modes:\n"
  194. " --start-dma <num>[r|w] - Start specified DMA engine\n"
  195. " --stop-dma [num[r|w]] - Stop specified engine or DMA subsystem\n"
  196. " --list-dma-engines - List active DMA engines\n"
  197. " --list-dma-buffers <dma> - List buffers for specified DMA engine\n"
  198. " --read-dma-buffer <dma:buf> - Read the specified buffer\n"
  199. " --wait-irq <source> - Wait for IRQ\n"
  200. "\n"
  201. " Kernel Modes:\n"
  202. " --list-kernel-memory - List kernel buffers\n"
  203. " --read-kernel-memory <blk> - Read the specified block of the kernel memory\n"
  204. " block is specified as: use:block_number\n"
  205. " --free-kernel-memory <use> - Cleans lost kernel space buffers (DANGEROUS)\n"
  206. " dma - Remove all buffers allocated by DMA subsystem\n"
  207. " #number - Remove all buffers with the specified use id\n"
  208. "\n"
  209. " Addressing:\n"
  210. " -d <device> - FPGA device (/dev/fpga0)\n"
  211. " -m <model> - Memory model (autodetected)\n"
  212. " pci - Plain\n"
  213. " ipecamera - IPE Camera\n"
  214. " -b <bank> - PCI bar, Register bank, or DMA channel\n"
  215. "\n"
  216. " Options:\n"
  217. " -s <size> - Number of words (default: 1)\n"
  218. " -a [fifo|dma]<bits> - Access type and bits per word (default: 32)\n"
  219. " -e <l|b> - Endianess Little/Big (default: host)\n"
  220. " -o <file> - Append output to file (default: stdout)\n"
  221. " -t <timeout|unlimited> - Timeout in microseconds\n"
  222. "\n"
  223. " Event Options:\n"
  224. " --event <evt> - Specifies event for trigger and grab modes\n"
  225. " --data <type> - Data type to request for the events\n"
  226. " --run-time <us> - Limit time to grab/trigger events\n"
  227. " -t <timeout|unlimited> - Timeout to stop if no events triggered\n"
  228. " --trigger-rate <tps> - Generate tps triggers per second\n"
  229. " --trigger-time <us> - Specifies delay between triggers (us)\n"
  230. " -s <num|unlimited> - Number of events to grab and trigger\n"
  231. " --format [type] - Specifies how event data should be stored\n"
  232. " raw - Just write all events sequentially\n"
  233. " add_header - Prefix events with 256 bit header\n"
  234. " ringfs - Write to RingFS\n"
  235. " --buffer [size] - Request data buffering, size in MB\n"
  236. "\n"
  237. " DMA Options:\n"
  238. " --multipacket - Read multiple packets\n"
  239. " --wait - Wait until data arrives\n"
  240. "\n"
  241. " Information:\n"
  242. " -q - Quiete mode (suppress warnings)\n"
  243. "\n"
  244. " Data:\n"
  245. " Data can be specified as sequence of hexdecimal number or\n"
  246. " a single value prefixed with '*'. In this case it will be\n"
  247. " replicated the specified amount of times\n"
  248. "\n\n",
  249. argv[0]);
  250. exit(0);
  251. }
  252. void Error(const char *format, ...) {
  253. va_list ap;
  254. va_start(ap, format);
  255. printf("Error %i: ", errno);
  256. vprintf(format, ap);
  257. if (errno) printf("\n errno: %s", strerror(errno));
  258. printf("\n\n");
  259. va_end(ap);
  260. exit(-1);
  261. }
  262. void Silence(const char *format, ...) {
  263. }
  264. void List(pcilib_t *handle, pcilib_model_description_t *model_info, const char *bank, int details) {
  265. int i,j;
  266. pcilib_register_bank_description_t *banks;
  267. pcilib_register_description_t *registers;
  268. pcilib_event_description_t *events;
  269. pcilib_event_data_type_description_t *types;
  270. const pcilib_board_info_t *board_info = pcilib_get_board_info(handle);
  271. const pcilib_dma_info_t *dma_info = pcilib_get_dma_info(handle);
  272. for (i = 0; i < PCILIB_MAX_BANKS; i++) {
  273. if (board_info->bar_length[i] > 0) {
  274. printf(" BAR %d - ", i);
  275. switch ( board_info->bar_flags[i]&IORESOURCE_TYPE_BITS) {
  276. case IORESOURCE_IO: printf(" IO"); break;
  277. case IORESOURCE_MEM: printf("MEM"); break;
  278. case IORESOURCE_IRQ: printf("IRQ"); break;
  279. case IORESOURCE_DMA: printf("DMA"); break;
  280. }
  281. if (board_info->bar_flags[i]&IORESOURCE_MEM_64) printf("64");
  282. else printf("32");
  283. printf(", Start: 0x%08lx, Length: 0x%8lx, Flags: 0x%08lx\n", board_info->bar_start[i], board_info->bar_length[i], board_info->bar_flags[i] );
  284. }
  285. }
  286. printf("\n");
  287. if ((dma_info)&&(dma_info->engines)) {
  288. printf("DMA Engines: \n");
  289. for (i = 0; dma_info->engines[i]; i++) {
  290. pcilib_dma_engine_description_t *engine = dma_info->engines[i];
  291. printf(" DMA %2d ", engine->addr);
  292. switch (engine->direction) {
  293. case PCILIB_DMA_FROM_DEVICE:
  294. printf("C2S");
  295. break;
  296. case PCILIB_DMA_TO_DEVICE:
  297. printf("S2C");
  298. break;
  299. case PCILIB_DMA_BIDIRECTIONAL:
  300. printf("BI ");
  301. break;
  302. }
  303. printf(" - Type: ");
  304. switch (engine->type) {
  305. case PCILIB_DMA_TYPE_BLOCK:
  306. printf("Block");
  307. break;
  308. case PCILIB_DMA_TYPE_PACKET:
  309. printf("Packet");
  310. break;
  311. default:
  312. printf("Unknown");
  313. }
  314. printf(", Address Width: %02lu bits\n", engine->addr_bits);
  315. }
  316. printf("\n");
  317. }
  318. if ((bank)&&(bank != (char*)-1)) banks = NULL;
  319. else banks = model_info->banks;
  320. if (banks) {
  321. printf("Banks: \n");
  322. for (i = 0; banks[i].access; i++) {
  323. printf(" 0x%02x %s", banks[i].addr, banks[i].name);
  324. if ((banks[i].description)&&(banks[i].description[0])) {
  325. printf(": %s", banks[i].description);
  326. }
  327. printf("\n");
  328. }
  329. printf("\n");
  330. }
  331. if (bank == (char*)-1) registers = NULL;
  332. else registers = model_info->registers;
  333. if (registers) {
  334. pcilib_register_bank_addr_t bank_addr = 0;
  335. if (bank) {
  336. pcilib_register_bank_t bank_id = pcilib_find_bank(handle, bank);
  337. pcilib_register_bank_description_t *b = model_info->banks + bank_id;
  338. bank_addr = b->addr;
  339. if (b->description) printf("%s:\n", b->description);
  340. else if (b->name) printf("Registers of bank %s:\n", b->name);
  341. else printf("Registers of bank 0x%x:\n", b->addr);
  342. } else {
  343. printf("Registers: \n");
  344. }
  345. for (i = 0; registers[i].bits; i++) {
  346. const char *mode;
  347. if ((bank)&&(registers[i].bank != bank_addr)) continue;
  348. if (registers[i].type == PCILIB_REGISTER_BITS) {
  349. if (!details) continue;
  350. if (registers[i].bits > 1) {
  351. printf(" [%2u:%2u] - %s\n", registers[i].offset, registers[i].offset + registers[i].bits, registers[i].name);
  352. } else {
  353. printf(" [ %2u] - %s\n", registers[i].offset, registers[i].name);
  354. }
  355. continue;
  356. }
  357. if (registers[i].mode == PCILIB_REGISTER_RW) mode = "RW";
  358. else if (registers[i].mode == PCILIB_REGISTER_R) mode = "R ";
  359. else if (registers[i].mode == PCILIB_REGISTER_W) mode = " W";
  360. else mode = " ";
  361. printf(" 0x%02x (%2i %s) %s", registers[i].addr, registers[i].bits, mode, registers[i].name);
  362. if ((details > 0)&&(registers[i].description)&&(registers[i].description[0])) {
  363. printf(": %s", registers[i].description);
  364. }
  365. printf("\n");
  366. }
  367. printf("\n");
  368. }
  369. if (bank == (char*)-1) events = NULL;
  370. else {
  371. events = model_info->events;
  372. types = model_info->data_types;
  373. }
  374. if (events) {
  375. printf("Events: \n");
  376. for (i = 0; events[i].name; i++) {
  377. printf(" %s", events[i].name);
  378. if ((events[i].description)&&(events[i].description[0])) {
  379. printf(": %s", events[i].description);
  380. }
  381. if (types) {
  382. for (j = 0; types[j].name; j++) {
  383. if (types[j].evid & events[i].evid) {
  384. printf("\n %s", types[j].name);
  385. if ((types[j].description)&&(types[j].description[0])) {
  386. printf(": %s", types[j].description);
  387. }
  388. }
  389. }
  390. }
  391. }
  392. printf("\n");
  393. }
  394. }
  395. void Info(pcilib_t *handle, pcilib_model_description_t *model_info) {
  396. const pcilib_board_info_t *board_info = pcilib_get_board_info(handle);
  397. printf("Vendor: %x, Device: %x, Interrupt Pin: %i, Interrupt Line: %i\n", board_info->vendor_id, board_info->device_id, board_info->interrupt_pin, board_info->interrupt_line);
  398. List(handle, model_info, (char*)-1, 0);
  399. }
  400. #define BENCH_MAX_DMA_SIZE 4 * 1024 * 1024
  401. #define BENCH_MAX_FIFO_SIZE 1024 * 1024
  402. int Benchmark(pcilib_t *handle, ACCESS_MODE mode, pcilib_dma_engine_addr_t dma, pcilib_bar_t bar, uintptr_t addr, size_t n, access_t access, size_t iterations) {
  403. int err;
  404. int i, j, errors;
  405. void *data, *buf, *check;
  406. void *fifo = NULL;
  407. struct timeval start, end;
  408. unsigned long time;
  409. size_t size, min_size, max_size;
  410. double mbs_in, mbs_out, mbs;
  411. size_t irqs;
  412. const pcilib_board_info_t *board_info = pcilib_get_board_info(handle);
  413. if (mode == ACCESS_DMA) {
  414. if (n) {
  415. min_size = n * access;
  416. max_size = n * access;
  417. } else {
  418. min_size = 1024;
  419. max_size = BENCH_MAX_DMA_SIZE;
  420. }
  421. for (size = min_size; size <= max_size; size *= 4) {
  422. mbs_in = pcilib_benchmark_dma(handle, dma, addr, size, iterations, PCILIB_DMA_FROM_DEVICE);
  423. mbs_out = pcilib_benchmark_dma(handle, dma, addr, size, iterations, PCILIB_DMA_TO_DEVICE);
  424. mbs = pcilib_benchmark_dma(handle, dma, addr, size, iterations, PCILIB_DMA_BIDIRECTIONAL);
  425. err = pcilib_wait_irq(handle, 0, 0, &irqs);
  426. if (err) irqs = 0;
  427. printf("%8zu KB - ", size / 1024);
  428. printf("RW: ");
  429. if (mbs < 0) printf("failed ... ");
  430. else printf("%8.2lf MB/s", mbs);
  431. printf(", R: ");
  432. if (mbs_in < 0) printf("failed ... ");
  433. else printf("%8.2lf MB/s", mbs_in);
  434. printf(", W: ");
  435. if (mbs_out < 0) printf("failed ... ");
  436. else printf("%8.2lf MB/s", mbs_out);
  437. if (irqs) {
  438. printf(", IRQs: %lu", irqs);
  439. }
  440. printf("\n");
  441. }
  442. return 0;
  443. }
  444. if (bar == PCILIB_BAR_INVALID) {
  445. unsigned long maxlength = 0;
  446. for (i = 0; i < PCILIB_MAX_BANKS; i++) {
  447. if ((addr >= board_info->bar_start[i])&&((board_info->bar_start[i] + board_info->bar_length[i]) >= (addr + access))) {
  448. bar = i;
  449. break;
  450. }
  451. if (board_info->bar_length[i] > maxlength) {
  452. maxlength = board_info->bar_length[i];
  453. bar = i;
  454. }
  455. }
  456. if (bar < 0) Error("Data banks are not available");
  457. }
  458. if (n) {
  459. if ((mode == ACCESS_BAR)&&(n * access > board_info->bar_length[bar])) Error("The specified size (%i) exceeds the size of bar (%i)", n * access, board_info->bar_length[bar]);
  460. min_size = n * access;
  461. max_size = n * access;
  462. } else {
  463. min_size = access;
  464. if (mode == ACCESS_BAR) max_size = board_info->bar_length[bar];
  465. else max_size = BENCH_MAX_FIFO_SIZE;
  466. }
  467. err = posix_memalign( (void**)&buf, 256, max_size );
  468. if (!err) err = posix_memalign( (void**)&check, 256, max_size );
  469. if ((err)||(!buf)||(!check)) Error("Allocation of %i bytes of memory have failed", max_size);
  470. data = pcilib_map_bar(handle, bar);
  471. if (!data) Error("Can't map bar %i", bar);
  472. if (mode == ACCESS_FIFO) {
  473. fifo = data + (addr - board_info->bar_start[bar]) + (board_info->bar_start[bar] & pcilib_get_page_mask());
  474. // pcilib_resolve_register_address(handle, bar, addr);
  475. if (!fifo) Error("Can't resolve address (%lx) in bar (%u)", addr, bar);
  476. }
  477. if (mode == ACCESS_FIFO)
  478. printf("Transfer time (Bank: %i, Fifo: %lx):\n", bar, addr);
  479. else
  480. printf("Transfer time (Bank: %i):\n", bar);
  481. for (size = min_size ; size < max_size; size *= 8) {
  482. gettimeofday(&start,NULL);
  483. if (mode == ACCESS_BAR) {
  484. for (i = 0; i < BENCHMARK_ITERATIONS; i++) {
  485. pcilib_memcpy(buf, data, size);
  486. }
  487. } else {
  488. for (i = 0; i < BENCHMARK_ITERATIONS; i++) {
  489. for (j = 0; j < (size/access); j++) {
  490. pcilib_memcpy(buf + j * access, fifo, access);
  491. }
  492. }
  493. }
  494. gettimeofday(&end,NULL);
  495. time = (end.tv_sec - start.tv_sec)*1000000 + (end.tv_usec - start.tv_usec);
  496. printf("%8zu bytes - read: %8.2lf MB/s", size, 1000000. * size * BENCHMARK_ITERATIONS / (time * 1024. * 1024.));
  497. fflush(0);
  498. gettimeofday(&start,NULL);
  499. if (mode == ACCESS_BAR) {
  500. for (i = 0; i < BENCHMARK_ITERATIONS; i++) {
  501. pcilib_memcpy(data, buf, size);
  502. }
  503. } else {
  504. for (i = 0; i < BENCHMARK_ITERATIONS; i++) {
  505. for (j = 0; j < (size/access); j++) {
  506. pcilib_memcpy(fifo, buf + j * access, access);
  507. }
  508. }
  509. }
  510. gettimeofday(&end,NULL);
  511. time = (end.tv_sec - start.tv_sec)*1000000 + (end.tv_usec - start.tv_usec);
  512. printf(", write: %8.2lf MB/s\n", 1000000. * size * BENCHMARK_ITERATIONS / (time * 1024. * 1024.));
  513. }
  514. pcilib_unmap_bar(handle, bar, data);
  515. printf("\n\nOpen-Transfer-Close time: \n");
  516. for (size = 4 ; size < max_size; size *= 8) {
  517. gettimeofday(&start,NULL);
  518. if (mode == ACCESS_BAR) {
  519. for (i = 0; i < BENCHMARK_ITERATIONS; i++) {
  520. pcilib_read(handle, bar, 0, size, buf);
  521. }
  522. } else {
  523. for (i = 0; i < BENCHMARK_ITERATIONS; i++) {
  524. pcilib_read_fifo(handle, bar, addr, access, size / access, buf);
  525. }
  526. }
  527. gettimeofday(&end,NULL);
  528. time = (end.tv_sec - start.tv_sec)*1000000 + (end.tv_usec - start.tv_usec);
  529. printf("%8zu bytes - read: %8.2lf MB/s", size, 1000000. * size * BENCHMARK_ITERATIONS / (time * 1024. * 1024.));
  530. fflush(0);
  531. gettimeofday(&start,NULL);
  532. if (mode == ACCESS_BAR) {
  533. for (i = 0; i < BENCHMARK_ITERATIONS; i++) {
  534. pcilib_write(handle, bar, 0, size, buf);
  535. }
  536. } else {
  537. for (i = 0; i < BENCHMARK_ITERATIONS; i++) {
  538. pcilib_write_fifo(handle, bar, addr, access, size / access, buf);
  539. }
  540. }
  541. gettimeofday(&end,NULL);
  542. time = (end.tv_sec - start.tv_sec)*1000000 + (end.tv_usec - start.tv_usec);
  543. printf(", write: %8.2lf MB/s", 1000000. * size * BENCHMARK_ITERATIONS / (time * 1024. * 1024.));
  544. if (mode == ACCESS_BAR) {
  545. gettimeofday(&start,NULL);
  546. for (i = 0, errors = 0; i < BENCHMARK_ITERATIONS; i++) {
  547. pcilib_write(handle, bar, 0, size, buf);
  548. pcilib_read(handle, bar, 0, size, check);
  549. if (memcmp(buf, check, size)) ++errors;
  550. }
  551. gettimeofday(&end,NULL);
  552. time = (end.tv_sec - start.tv_sec)*1000000 + (end.tv_usec - start.tv_usec);
  553. printf(", write-verify: %8.2lf MB/s", 1000000. * size * BENCHMARK_ITERATIONS / (time * 1024. * 1024.));
  554. if (errors) printf(", errors: %u of %u", errors, BENCHMARK_ITERATIONS);
  555. }
  556. printf("\n");
  557. }
  558. printf("\n\n");
  559. free(check);
  560. free(buf);
  561. return 0;
  562. }
  563. #define pci2host16(endianess, value) endianess?
  564. /*
  565. typedef struct {
  566. size_t size;
  567. void *data;
  568. size_t pos;
  569. int multi_mode;
  570. } DMACallbackContext;
  571. static int DMACallback(void *arg, pcilib_dma_flags_t flags, size_t bufsize, void *buf) {
  572. DMACallbackContext *ctx = (DMACallbackContext*)arg;
  573. if ((ctx->pos + bufsize > ctx->size)||(!ctx->data)) {
  574. ctx->size *= 2;
  575. ctx->data = realloc(ctx->data, ctx->size);
  576. if (!ctx->data) {
  577. Error("Allocation of %i bytes of memory have failed", ctx->size);
  578. return 0;
  579. }
  580. }
  581. memcpy(ctx->data + ctx->pos, buf, bufsize);
  582. ctx->pos += bufsize;
  583. if (flags & PCILIB_DMA_FLAG_EOP) return 0;
  584. return 1;
  585. }
  586. */
  587. int ReadData(pcilib_t *handle, ACCESS_MODE mode, FLAGS flags, pcilib_dma_engine_addr_t dma, pcilib_bar_t bar, uintptr_t addr, size_t n, access_t access, int endianess, size_t timeout, FILE *o) {
  588. void *buf;
  589. int i, err;
  590. size_t ret, bytes;
  591. size_t size = n * abs(access);
  592. int block_width, blocks_per_line;
  593. int numbers_per_block, numbers_per_line;
  594. pcilib_dma_engine_t dmaid;
  595. pcilib_dma_flags_t dma_flags = 0;
  596. numbers_per_block = BLOCK_SIZE / access;
  597. block_width = numbers_per_block * ((access * 2) + SEPARATOR_WIDTH);
  598. blocks_per_line = (LINE_WIDTH - 10) / (block_width + BLOCK_SEPARATOR_WIDTH);
  599. if ((blocks_per_line > 1)&&(blocks_per_line % 2)) --blocks_per_line;
  600. numbers_per_line = blocks_per_line * numbers_per_block;
  601. if (size) {
  602. buf = malloc(size);
  603. if (!buf) Error("Allocation of %zu bytes of memory has failed", size);
  604. } else {
  605. buf = NULL;
  606. }
  607. switch (mode) {
  608. case ACCESS_DMA:
  609. if (timeout == (size_t)-1) timeout = PCILIB_DMA_TIMEOUT;
  610. dmaid = pcilib_find_dma_by_addr(handle, PCILIB_DMA_FROM_DEVICE, dma);
  611. if (dmaid == PCILIB_DMA_ENGINE_INVALID) Error("Invalid DMA engine (%lu) is specified", dma);
  612. if (flags&FLAG_MULTIPACKET) dma_flags |= PCILIB_DMA_FLAG_MULTIPACKET;
  613. if (flags&FLAG_WAIT) dma_flags |= PCILIB_DMA_FLAG_WAIT;
  614. if (size) {
  615. err = pcilib_read_dma_custom(handle, dmaid, addr, size, dma_flags, timeout, buf, &bytes);
  616. if (err) Error("Error (%i) is reported by DMA engine", err);
  617. } else {
  618. dma_flags |= PCILIB_DMA_FLAG_IGNORE_ERRORS;
  619. size = 2048; bytes = 0;
  620. do {
  621. size *= 2;
  622. buf = realloc(buf, size);
  623. if (!buf) Error("Allocation of %zu bytes of memory has failed", size);
  624. err = pcilib_read_dma_custom(handle, dmaid, addr, size - bytes, dma_flags, timeout, buf + bytes, &ret);
  625. bytes += ret;
  626. if ((!err)&&(flags&FLAG_MULTIPACKET)) {
  627. err = PCILIB_ERROR_TOOBIG;
  628. if ((flags&FLAG_WAIT)==0) timeout = 0;
  629. }
  630. } while (err == PCILIB_ERROR_TOOBIG);
  631. }
  632. if (bytes <= 0) Error("No data is returned by DMA engine");
  633. size = bytes;
  634. n = bytes / abs(access);
  635. addr = 0;
  636. break;
  637. case ACCESS_FIFO:
  638. pcilib_read_fifo(handle, bar, addr, access, n, buf);
  639. addr = 0;
  640. break;
  641. default:
  642. pcilib_read(handle, bar, addr, size, buf);
  643. }
  644. if (endianess) pcilib_swap(buf, buf, abs(access), n);
  645. if (o) {
  646. printf("Writting output (%zu bytes) to file (append to the end)...\n", n * abs(access));
  647. fwrite(buf, abs(access), n, o);
  648. } else {
  649. for (i = 0; i < n; i++) {
  650. if (i) {
  651. if (i%numbers_per_line == 0) printf("\n");
  652. else {
  653. printf("%*s", SEPARATOR_WIDTH, "");
  654. if (i%numbers_per_block == 0) printf("%*s", BLOCK_SEPARATOR_WIDTH, "");
  655. }
  656. }
  657. if (i%numbers_per_line == 0) printf("%8lx: ", addr + i * abs(access));
  658. switch (access) {
  659. case 1: printf("%0*hhx", access * 2, ((uint8_t*)buf)[i]); break;
  660. case 2: printf("%0*hx", access * 2, ((uint16_t*)buf)[i]); break;
  661. case 4: printf("%0*x", access * 2, ((uint32_t*)buf)[i]); break;
  662. case 8: printf("%0*lx", access * 2, ((uint64_t*)buf)[i]); break;
  663. }
  664. }
  665. printf("\n\n");
  666. }
  667. free(buf);
  668. return 0;
  669. }
  670. int ReadRegister(pcilib_t *handle, pcilib_model_description_t *model_info, const char *bank, const char *reg) {
  671. int i;
  672. int err;
  673. const char *format;
  674. pcilib_register_bank_t bank_id;
  675. pcilib_register_bank_addr_t bank_addr = 0;
  676. pcilib_register_value_t value;
  677. if (reg) {
  678. pcilib_register_t regid = pcilib_find_register(handle, bank, reg);
  679. bank_id = pcilib_find_bank_by_addr(handle, model_info->registers[regid].bank);
  680. format = model_info->banks[bank_id].format;
  681. if (!format) format = "%lu";
  682. err = pcilib_read_register_by_id(handle, regid, &value);
  683. // err = pcilib_read_register(handle, bank, reg, &value);
  684. if (err) printf("Error reading register %s\n", reg);
  685. else {
  686. printf("%s = ", reg);
  687. printf(format, value);
  688. printf("\n");
  689. }
  690. } else {
  691. // Adding DMA registers
  692. pcilib_get_dma_info(handle);
  693. if (model_info->registers) {
  694. if (bank) {
  695. bank_id = pcilib_find_bank(handle, bank);
  696. bank_addr = model_info->banks[bank_id].addr;
  697. }
  698. printf("Registers:\n");
  699. for (i = 0; model_info->registers[i].bits; i++) {
  700. if ((model_info->registers[i].mode & PCILIB_REGISTER_R)&&((!bank)||(model_info->registers[i].bank == bank_addr))&&(model_info->registers[i].type != PCILIB_REGISTER_BITS)) {
  701. bank_id = pcilib_find_bank_by_addr(handle, model_info->registers[i].bank);
  702. format = model_info->banks[bank_id].format;
  703. if (!format) format = "%lu";
  704. err = pcilib_read_register_by_id(handle, i, &value);
  705. if (err) printf(" %s = error reading value", model_info->registers[i].name);
  706. else {
  707. printf(" %s = ", model_info->registers[i].name);
  708. printf(format, value);
  709. }
  710. printf(" [");
  711. printf(format, model_info->registers[i].defvalue);
  712. printf("]");
  713. printf("\n");
  714. }
  715. }
  716. } else {
  717. printf("No registers");
  718. }
  719. printf("\n");
  720. }
  721. return 0;
  722. }
  723. #define WRITE_REGVAL(buf, n, access, o) {\
  724. uint##access##_t tbuf[n]; \
  725. for (i = 0; i < n; i++) { \
  726. tbuf[i] = (uint##access##_t)buf[i]; \
  727. } \
  728. fwrite(tbuf, access/8, n, o); \
  729. }
  730. int ReadRegisterRange(pcilib_t *handle, pcilib_model_description_t *model_info, const char *bank, uintptr_t addr, long addr_shift, size_t n, FILE *o) {
  731. int err;
  732. int i;
  733. pcilib_register_bank_description_t *banks = model_info->banks;
  734. pcilib_register_bank_t bank_id = pcilib_find_bank(handle, bank);
  735. if (bank_id == PCILIB_REGISTER_BANK_INVALID) {
  736. if (bank) Error("Invalid register bank is specified (%s)", bank);
  737. else Error("Register bank should be specified");
  738. }
  739. int access = banks[bank_id].access / 8;
  740. // int size = n * abs(access);
  741. int block_width, blocks_per_line;
  742. int numbers_per_block, numbers_per_line;
  743. numbers_per_block = BLOCK_SIZE / access;
  744. block_width = numbers_per_block * ((access * 2) + SEPARATOR_WIDTH);
  745. blocks_per_line = (LINE_WIDTH - 6) / (block_width + BLOCK_SEPARATOR_WIDTH);
  746. if ((blocks_per_line > 1)&&(blocks_per_line % 2)) --blocks_per_line;
  747. numbers_per_line = blocks_per_line * numbers_per_block;
  748. pcilib_register_value_t buf[n];
  749. err = pcilib_read_register_space(handle, bank, addr, n, buf);
  750. if (err) Error("Error reading register space for bank \"%s\" at address %lx, size %lu", bank?bank:"default", addr, n);
  751. if (o) {
  752. printf("Writting output (%zu bytes) to file (append to the end)...\n", n * abs(access));
  753. switch (access) {
  754. case 1: WRITE_REGVAL(buf, n, 8, o) break;
  755. case 2: WRITE_REGVAL(buf, n, 16, o) break;
  756. case 4: WRITE_REGVAL(buf, n, 32, o) break;
  757. case 8: WRITE_REGVAL(buf, n, 64, o) break;
  758. }
  759. } else {
  760. for (i = 0; i < n; i++) {
  761. if (i) {
  762. if (i%numbers_per_line == 0) printf("\n");
  763. else {
  764. printf("%*s", SEPARATOR_WIDTH, "");
  765. if (i%numbers_per_block == 0) printf("%*s", BLOCK_SEPARATOR_WIDTH, "");
  766. }
  767. }
  768. if (i%numbers_per_line == 0) printf("%4lx: ", addr + i - addr_shift);
  769. printf("%0*lx", access * 2, (unsigned long)buf[i]);
  770. }
  771. printf("\n\n");
  772. }
  773. return 0;
  774. }
  775. int WriteData(pcilib_t *handle, ACCESS_MODE mode, pcilib_dma_engine_addr_t dma, pcilib_bar_t bar, uintptr_t addr, size_t n, access_t access, int endianess, char ** data) {
  776. int read_back = 0;
  777. void *buf, *check;
  778. int res = 0, i, err;
  779. int size = n * abs(access);
  780. size_t ret;
  781. pcilib_dma_engine_t dmaid;
  782. err = posix_memalign( (void**)&buf, 256, size );
  783. if (!err) err = posix_memalign( (void**)&check, 256, size );
  784. if ((err)||(!buf)||(!check)) Error("Allocation of %i bytes of memory have failed", size);
  785. for (i = 0; i < n; i++) {
  786. switch (access) {
  787. case 1: res = sscanf(data[i], "%hhx", ((uint8_t*)buf)+i); break;
  788. case 2: res = sscanf(data[i], "%hx", ((uint16_t*)buf)+i); break;
  789. case 4: res = sscanf(data[i], "%x", ((uint32_t*)buf)+i); break;
  790. case 8: res = sscanf(data[i], "%lx", ((uint64_t*)buf)+i); break;
  791. default: Error("Unexpected data size (%lu)", access);
  792. }
  793. if ((res != 1)||(!isxnumber(data[i]))) Error("Can't parse data value at poition %i, (%s) is not valid hex number", i, data[i]);
  794. }
  795. if (endianess) pcilib_swap(buf, buf, abs(access), n);
  796. switch (mode) {
  797. case ACCESS_DMA:
  798. dmaid = pcilib_find_dma_by_addr(handle, PCILIB_DMA_TO_DEVICE, dma);
  799. if (dmaid == PCILIB_DMA_ENGINE_INVALID) Error("Invalid DMA engine (%lu) is specified", dma);
  800. err = pcilib_write_dma(handle, dmaid, addr, size, buf, &ret);
  801. if ((err)||(ret != size)) {
  802. if (err == PCILIB_ERROR_TIMEOUT) Error("Timeout writting the data to DMA");
  803. else if (err) Error("DMA engine returned a error while writing the data");
  804. else if (!ret) Error("No data is written by DMA engine");
  805. else Error("Only %lu bytes of %lu is written by DMA engine", ret, size);
  806. }
  807. break;
  808. case ACCESS_FIFO:
  809. pcilib_write_fifo(handle, bar, addr, access, n, buf);
  810. break;
  811. default:
  812. pcilib_write(handle, bar, addr, size, buf);
  813. pcilib_read(handle, bar, addr, size, check);
  814. read_back = 1;
  815. }
  816. if ((read_back)&&(memcmp(buf, check, size))) {
  817. printf("Write failed: the data written and read differ, the foolowing is read back:\n");
  818. if (endianess) pcilib_swap(check, check, abs(access), n);
  819. ReadData(handle, mode, 0, dma, bar, addr, n, access, endianess, (size_t)-1, NULL);
  820. exit(-1);
  821. }
  822. free(check);
  823. free(buf);
  824. return 0;
  825. }
  826. int WriteRegisterRange(pcilib_t *handle, pcilib_model_description_t *model_info, const char *bank, uintptr_t addr, long addr_shift, size_t n, char ** data) {
  827. pcilib_register_value_t *buf, *check;
  828. int res, i, err;
  829. unsigned long value;
  830. int size = n * sizeof(pcilib_register_value_t);
  831. err = posix_memalign( (void**)&buf, 256, size );
  832. if (!err) err = posix_memalign( (void**)&check, 256, size );
  833. if ((err)||(!buf)||(!check)) Error("Allocation of %i bytes of memory have failed", size);
  834. for (i = 0; i < n; i++) {
  835. res = sscanf(data[i], "%lx", &value);
  836. if ((res != 1)||(!isxnumber(data[i]))) Error("Can't parse data value at poition %i, (%s) is not valid hex number", i, data[i]);
  837. buf[i] = value;
  838. }
  839. err = pcilib_write_register_space(handle, bank, addr, n, buf);
  840. if (err) Error("Error writting register space for bank \"%s\" at address %lx, size %lu", bank?bank:"default", addr, n);
  841. err = pcilib_read_register_space(handle, bank, addr, n, check);
  842. if (err) Error("Error reading register space for bank \"%s\" at address %lx, size %lu", bank?bank:"default", addr, n);
  843. if (memcmp(buf, check, size)) {
  844. printf("Write failed: the data written and read differ, the foolowing is read back:\n");
  845. ReadRegisterRange(handle, model_info, bank, addr, addr_shift, n, NULL);
  846. exit(-1);
  847. }
  848. free(check);
  849. free(buf);
  850. return 0;
  851. }
  852. int WriteRegister(pcilib_t *handle, pcilib_model_description_t *model_info, const char *bank, const char *reg, char ** data) {
  853. int err;
  854. unsigned long val;
  855. pcilib_register_value_t value;
  856. const char *format = NULL;
  857. pcilib_register_t regid = pcilib_find_register(handle, bank, reg);
  858. if (regid == PCILIB_REGISTER_INVALID) Error("Can't find register (%s) from bank (%s)", reg, bank?bank:"autodetected");
  859. /*
  860. pcilib_register_bank_t bank_id;
  861. pcilib_register_bank_addr_t bank_addr;
  862. bank_id = pcilib_find_bank_by_addr(handle, model_info->registers[regid].bank);
  863. if (bank_id == PCILIB_REGISTER_BANK_INVALID) Error("Can't find bank of the register (%s)", reg);
  864. format = model_info->banks[bank_id].format;
  865. if (!format) format = "%lu";
  866. */
  867. if (isnumber(*data)) {
  868. if (sscanf(*data, "%li", &val) != 1) {
  869. Error("Can't parse data value (%s) is not valid decimal number", *data);
  870. }
  871. format = "%li";
  872. } else if (isxnumber(*data)) {
  873. if (sscanf(*data, "%lx", &val) != 1) {
  874. Error("Can't parse data value (%s) is not valid decimal number", *data);
  875. }
  876. format = "0x%lx";
  877. } else {
  878. Error("Can't parse data value (%s) is not valid decimal number", *data);
  879. }
  880. value = val;
  881. err = pcilib_write_register(handle, bank, reg, value);
  882. if (err) Error("Error writting register %s\n", reg);
  883. if ((model_info->registers[regid].mode&PCILIB_REGISTER_RW) == PCILIB_REGISTER_RW) {
  884. err = pcilib_read_register(handle, bank, reg, &value);
  885. if (err) Error("Error reading back register %s for verification\n", reg);
  886. if (val != value) {
  887. Error("Failed to write register %s: %lu is written and %lu is read back", reg, val, value);
  888. } else {
  889. printf("%s = ", reg);
  890. printf(format, value);
  891. printf("\n");
  892. }
  893. } else {
  894. printf("%s is written\n ", reg);
  895. }
  896. return 0;
  897. }
  898. typedef struct {
  899. pcilib_t *handle;
  900. pcilib_event_t event;
  901. pcilib_event_data_type_t data;
  902. FILE *output;
  903. pcilib_timeout_t timeout;
  904. size_t run_time;
  905. size_t trigger_time;
  906. size_t max_triggers;
  907. int event_pending; /**< Used to detect that we have read previously triggered event */
  908. int trigger_thread_started; /**< Indicates that trigger thread is ready and we can't procced to start event recording */
  909. int started; /**< Indicates that recording is started */
  910. int run_flag;
  911. struct timeval first_frame;
  912. struct timeval last_frame;
  913. size_t trigger_count;
  914. size_t event_count;
  915. size_t broken_count;
  916. struct timeval start_time;
  917. struct timeval stop_time;
  918. } GRABContext;
  919. #include "ipecamera/ipecamera.h"
  920. int GrabCallback(pcilib_event_id_t event_id, pcilib_event_info_t *info, void *user) {
  921. int err;
  922. void *data;
  923. size_t size, written;
  924. GRABContext *ctx = (GRABContext*)user;
  925. pcilib_t *handle = ctx->handle;
  926. ipecamera_event_info_t *ipe = (ipecamera_event_info_t*)info;
  927. gettimeofday(&ctx->last_frame, NULL);
  928. if (!ctx->event_count) {
  929. memcpy(&ctx->first_frame, &ctx->last_frame, sizeof(struct timeval));
  930. }
  931. ctx->event_pending = 0;
  932. ctx->event_count++;
  933. if (info->flags&PCILIB_EVENT_INFO_FLAG_BROKEN) {
  934. ctx->broken_count++;
  935. return PCILIB_STREAMING_CONTINUE;
  936. }
  937. data = pcilib_get_data(handle, event_id, ctx->data, &size);
  938. if (!data) {
  939. ctx->broken_count++;
  940. return PCILIB_STREAMING_CONTINUE;
  941. }
  942. //Error("Internal Error: No data is provided to event callback");
  943. written = fwrite(data, 1, size, ctx->output);
  944. if (written != size) {
  945. if (written > 0) Error("Write failed, only %z bytes out of %z are stored", written, size);
  946. else Error("Write failed");
  947. }
  948. pcilib_return_data(handle, event_id, ctx->data, data);
  949. // printf("%lu %lu\n", info->seqnum, info->offset);
  950. // printf("%lu %lx %lu\n", ipe->raw_size, info->flags, ctx->broken_count);
  951. /*
  952. FILE *o = ctx->output;
  953. data = pcilib_get_data(handle, ctx->event, ctx->data, &size);
  954. if (!data) Error("Internal Error: No data is provided to event callback");
  955. if (o) printf("Writting %zu bytes into file...\n", size);
  956. else o = stdout;
  957. written = fwrite(data, 1, size, o);
  958. if (written != size) {
  959. if (written > 0) Error("Write failed, only %z bytes out of %z are stored", written, size);
  960. else Error("Write failed");
  961. }
  962. pcilib_return_data(handle, ctx->event, data);
  963. */
  964. // printf("data callback: %lu\n", event_id);
  965. return PCILIB_STREAMING_CONTINUE;
  966. }
  967. int raw_data(pcilib_event_id_t event_id, pcilib_event_info_t *info, pcilib_event_flags_t flags, size_t size, void *data, void *user) {
  968. // printf("%i\n", event_id);
  969. return PCILIB_STREAMING_CONTINUE;
  970. }
  971. void *Trigger(void *user) {
  972. struct timeval start;
  973. GRABContext *ctx = (GRABContext*)user;
  974. size_t trigger_time = ctx->trigger_time;
  975. size_t max_triggers = ctx->max_triggers;
  976. ctx->trigger_thread_started = 1;
  977. ctx->event_pending = 1;
  978. while (!ctx->started);
  979. gettimeofday(&start, NULL);
  980. do {
  981. pcilib_trigger(ctx->handle, ctx->event, 0, NULL);
  982. if ((++ctx->trigger_count == max_triggers)&&(max_triggers)) break;
  983. if (trigger_time) {
  984. pcilib_add_timeout(&start, trigger_time);
  985. if ((ctx->stop_time.tv_sec)&&(pcilib_timecmp(&start, &ctx->stop_time)>0)) break;
  986. pcilib_sleep_until_deadline(&start);
  987. } else {
  988. while ((ctx->event_pending)&&(ctx->run_flag)) usleep(10);
  989. ctx->event_pending = 1;
  990. }
  991. } while (ctx->run_flag);
  992. ctx->trigger_thread_started = 0;
  993. return NULL;
  994. }
  995. void GrabStats(GRABContext *ctx, struct timeval *end_time) {
  996. pcilib_timeout_t duration, fps_duration;
  997. struct timeval cur;
  998. double fps = 0;
  999. if (!end_time) {
  1000. gettimeofday(&cur, NULL);
  1001. end_time = &cur;
  1002. }
  1003. duration = pcilib_timediff(&ctx->start_time, end_time);
  1004. if (ctx->event_count > 1) {
  1005. fps_duration = pcilib_timediff(&ctx->first_frame, &ctx->last_frame);
  1006. fps = (ctx->event_count - 1) / (1.*fps_duration/1000000);
  1007. }
  1008. if (duration > 100000000) printf("Time: %9lu s", duration/1000000);
  1009. else if (duration > 10000000) printf("Time: %9.1lf s", 1.*duration/1000000);
  1010. else if (duration > 1000000) printf("Time: %9.2lf s", 1.*duration/1000000);
  1011. else if (duration > 1000) printf("Time: %9lu ms", duration/1000);
  1012. else printf("Time: %9lu us", duration);
  1013. printf(", Triggers: %9lu, Frames: %9lu, Broken: %9u, Lost: %9u, FPS: %5.1lf\n", ctx->trigger_count, ctx->event_count, ctx->broken_count, 0, fps);
  1014. }
  1015. void *Monitor(void *user) {
  1016. struct timeval deadline;
  1017. GRABContext *ctx = (GRABContext*)user;
  1018. pcilib_timeout_t timeout = ctx->timeout;
  1019. if (timeout == PCILIB_TIMEOUT_INFINITE) timeout = 0;
  1020. // while (!ctx->started);
  1021. if (timeout) {
  1022. memcpy(&deadline, &ctx->last_frame, sizeof(struct timeval));
  1023. pcilib_add_timeout(&deadline, timeout);
  1024. }
  1025. while (ctx->run_flag) {
  1026. if (timeout) {
  1027. if (pcilib_calc_time_to_deadline(&deadline) == 0) {
  1028. memcpy(&deadline, &ctx->last_frame, sizeof(struct timeval));
  1029. pcilib_add_timeout(&deadline, timeout);
  1030. if (pcilib_calc_time_to_deadline(&deadline) == 0) {
  1031. pcilib_stop(ctx->handle, PCILIB_EVENT_FLAG_STOP_ONLY);
  1032. break;
  1033. }
  1034. }
  1035. }
  1036. usleep(100000);
  1037. }
  1038. return NULL;
  1039. }
  1040. int TriggerAndGrab(pcilib_t *handle, GRAB_MODE grab_mode, const char *evname, const char *data_type, size_t num, size_t run_time, size_t trigger_time, pcilib_timeout_t timeout, PARTITION partition, FORMAT format, size_t buffer_size, FILE *ofile) {
  1041. int err;
  1042. GRABContext ctx;
  1043. // void *data = NULL;
  1044. // size_t size, written;
  1045. pcilib_event_t event;
  1046. pcilib_event_t listen_events;
  1047. pcilib_event_data_type_t data;
  1048. pthread_t monitor_thread;
  1049. pthread_t trigger_thread;
  1050. pthread_attr_t attr;
  1051. struct sched_param sched;
  1052. struct timeval end_time;
  1053. pcilib_event_flags_t flags;
  1054. if (evname) {
  1055. event = pcilib_find_event(handle, evname);
  1056. if (event == PCILIB_EVENT_INVALID)
  1057. Error("Can't find event (%s)", evname);
  1058. listen_events = event;
  1059. } else {
  1060. listen_events = PCILIB_EVENTS_ALL;
  1061. event = PCILIB_EVENT0;
  1062. }
  1063. if (data_type) {
  1064. data = pcilib_find_event_data_type(handle, event, data_type);
  1065. if (data == PCILIB_EVENT_DATA_TYPE_INVALID)
  1066. Error("Can't find data type (%s)", data_type);
  1067. } else {
  1068. data = PCILIB_EVENT_DATA;
  1069. }
  1070. ctx.handle = handle;
  1071. ctx.output = ofile;
  1072. ctx.event = event;
  1073. ctx.data = data;
  1074. ctx.run_time = run_time;
  1075. ctx.timeout = timeout;
  1076. ctx.event_count = 0;
  1077. ctx.broken_count = 0;
  1078. ctx.started = 0;
  1079. ctx.trigger_thread_started = 0;
  1080. ctx.run_flag = 1;
  1081. memset(&ctx.stop_time, 0, sizeof(struct timeval));
  1082. // printf("Limits: %lu %lu %lu\n", num, run_time, timeout);
  1083. pcilib_configure_autostop(handle, num, run_time);//PCILIB_TIMEOUT_TRIGGER);
  1084. pcilib_configure_rawdata_callback(handle, &raw_data, NULL);
  1085. flags = PCILIB_EVENT_FLAGS_DEFAULT;
  1086. // PCILIB_EVENT_FLAG_RAW_DATA_ONLY
  1087. if (grab_mode&GRAB_MODE_TRIGGER) {
  1088. if (!trigger_time) {
  1089. // Otherwise, we will trigger next event after previous one is read
  1090. if (((grab_mode&GRAB_MODE_GRAB) == 0)&&((flags&PCILIB_EVENT_FLAG_RAW_DATA_ONLY)==0)) trigger_time = PCILIB_TRIGGER_TIMEOUT;
  1091. }
  1092. ctx.max_triggers = num;
  1093. ctx.trigger_count = 0;
  1094. ctx.trigger_time = trigger_time;
  1095. // We don't really care if RT priority is imposible
  1096. pthread_attr_init(&attr);
  1097. if (!pthread_attr_setschedpolicy(&attr, SCHED_FIFO)) {
  1098. sched.sched_priority = sched_get_priority_min(SCHED_FIFO);
  1099. pthread_attr_setschedparam(&attr, &sched);
  1100. }
  1101. // Start triggering thread and wait until it is schedulled
  1102. if (pthread_create(&trigger_thread, &attr, Trigger, (void*)&ctx))
  1103. Error("Error spawning trigger thread");
  1104. while (!ctx.trigger_thread_started) usleep(10);
  1105. }
  1106. gettimeofday(&ctx.start_time, NULL);
  1107. if (grab_mode&GRAB_MODE_GRAB) {
  1108. err = pcilib_start(handle, listen_events, flags);
  1109. if (err) Error("Failed to start event engine, error %i", err);
  1110. }
  1111. ctx.started = 1;
  1112. if (run_time) {
  1113. ctx.stop_time.tv_usec = ctx.start_time.tv_usec + run_time%1000000;
  1114. if (ctx.stop_time.tv_usec > 999999) {
  1115. ctx.stop_time.tv_usec -= 1000000;
  1116. __sync_synchronize();
  1117. ctx.stop_time.tv_sec = ctx.start_time.tv_sec + 1 + run_time / 1000000;
  1118. } else {
  1119. __sync_synchronize();
  1120. ctx.stop_time.tv_sec = ctx.start_time.tv_sec + run_time / 1000000;
  1121. }
  1122. }
  1123. memcpy(&ctx.last_frame, &ctx.start_time, sizeof(struct timeval));
  1124. if (pthread_create(&monitor_thread, NULL, Monitor, (void*)&ctx))
  1125. Error("Error spawning monitoring thread");
  1126. if (grab_mode&GRAB_MODE_GRAB) {
  1127. err = pcilib_stream(handle, &GrabCallback, &ctx);
  1128. if (err) Error("Error streaming events, error %i", err);
  1129. }
  1130. ctx.run_flag = 0;
  1131. if (grab_mode&GRAB_MODE_TRIGGER) {
  1132. while (ctx.trigger_thread_started) usleep(10);
  1133. }
  1134. if (grab_mode&GRAB_MODE_GRAB) {
  1135. pcilib_stop(handle, PCILIB_EVENT_FLAGS_DEFAULT);
  1136. }
  1137. gettimeofday(&end_time, NULL);
  1138. /*
  1139. err = pcilib_grab(handle, PCILIB_EVENTS_ALL, &size, &data, PCILIB_TIMEOUT_TRIGGER);
  1140. if (err) {
  1141. Error("Grabbing event is failed");
  1142. }
  1143. */
  1144. pthread_join(monitor_thread, NULL);
  1145. if (grab_mode&GRAB_MODE_TRIGGER) {
  1146. pthread_join(trigger_thread, NULL);
  1147. }
  1148. GrabStats(&ctx, &end_time);
  1149. // print information
  1150. return 0;
  1151. }
  1152. /*
  1153. int Trigger(pcilib_t *handle, const char *event, size_t triggers, size_t run_time, size_t trigger_time) {
  1154. //
  1155. }
  1156. */
  1157. int StartStopDMA(pcilib_t *handle, pcilib_model_description_t *model_info, pcilib_dma_engine_addr_t dma, pcilib_dma_direction_t dma_direction, int start) {
  1158. int err;
  1159. pcilib_dma_engine_t dmaid;
  1160. if (dma == PCILIB_DMA_ENGINE_ADDR_INVALID) {
  1161. const pcilib_dma_info_t *dma_info = pcilib_get_dma_info(handle);
  1162. if (start) Error("DMA engine should be specified");
  1163. for (dmaid = 0; dma_info->engines[dmaid]; dmaid++) {
  1164. err = pcilib_start_dma(handle, dmaid, 0);
  1165. if (err) Error("Error starting DMA Engine (%s %i)", ((dma_info->engines[dmaid]->direction == PCILIB_DMA_FROM_DEVICE)?"C2S":"S2C"), dma_info->engines[dmaid]->addr);
  1166. err = pcilib_stop_dma(handle, dmaid, PCILIB_DMA_FLAG_PERSISTENT);
  1167. if (err) Error("Error stopping DMA Engine (%s %i)", ((dma_info->engines[dmaid]->direction == PCILIB_DMA_FROM_DEVICE)?"C2S":"S2C"), dma_info->engines[dmaid]->addr);
  1168. }
  1169. return 0;
  1170. }
  1171. if (dma_direction&PCILIB_DMA_FROM_DEVICE) {
  1172. dmaid = pcilib_find_dma_by_addr(handle, PCILIB_DMA_FROM_DEVICE, dma);
  1173. if (dmaid == PCILIB_DMA_ENGINE_INVALID) Error("Invalid DMA engine (C2S %lu) is specified", dma);
  1174. if (start) {
  1175. err = pcilib_start_dma(handle, dmaid, PCILIB_DMA_FLAG_PERSISTENT);
  1176. if (err) Error("Error starting DMA engine (C2S %lu)", dma);
  1177. } else {
  1178. err = pcilib_start_dma(handle, dmaid, 0);
  1179. if (err) Error("Error starting DMA engine (C2S %lu)", dma);
  1180. err = pcilib_stop_dma(handle, dmaid, PCILIB_DMA_FLAG_PERSISTENT);
  1181. if (err) Error("Error stopping DMA engine (C2S %lu)", dma);
  1182. }
  1183. }
  1184. if (dma_direction&PCILIB_DMA_TO_DEVICE) {
  1185. dmaid = pcilib_find_dma_by_addr(handle, PCILIB_DMA_TO_DEVICE, dma);
  1186. if (dmaid == PCILIB_DMA_ENGINE_INVALID) Error("Invalid DMA engine (S2C %lu) is specified", dma);
  1187. if (start) {
  1188. err = pcilib_start_dma(handle, dmaid, PCILIB_DMA_FLAG_PERSISTENT);
  1189. if (err) Error("Error starting DMA engine (S2C %lu)", dma);
  1190. } else {
  1191. err = pcilib_start_dma(handle, dmaid, 0);
  1192. if (err) Error("Error starting DMA engine (S2C %lu)", dma);
  1193. err = pcilib_stop_dma(handle, dmaid, PCILIB_DMA_FLAG_PERSISTENT);
  1194. if (err) Error("Error stopping DMA engine (S2C %lu)", dma);
  1195. }
  1196. }
  1197. return 0;
  1198. }
  1199. typedef struct {
  1200. unsigned long use;
  1201. int referenced;
  1202. int hw_lock;
  1203. int reusable;
  1204. int persistent;
  1205. int open;
  1206. size_t count;
  1207. size_t size;
  1208. } kmem_use_info_t;
  1209. #define MAX_USES 64
  1210. size_t FindUse(size_t *n_uses, kmem_use_info_t *uses, unsigned long use) {
  1211. size_t i, n = *n_uses;
  1212. if (uses[n - 1].use == use) return n - 1;
  1213. for (i = 1; i < (n - 1); i++) {
  1214. if (uses[i].use == use) return i;
  1215. }
  1216. if (n == MAX_USES) return 0;
  1217. uses[n].use = use;
  1218. return (*n_uses)++;
  1219. }
  1220. char *PrintSize(char *str, size_t size) {
  1221. if (size >= 1073741824) sprintf(str, "%.1lf GB", 1.*size / 1073741824);
  1222. else if (size >= 1048576) sprintf(str, "%.1lf MB", 1.*size / 1048576);
  1223. else if (size >= 1024) sprintf(str, "%lu KB", size / 1024);
  1224. else sprintf(str, "%lu B ", size);
  1225. return str;
  1226. }
  1227. int ListKMEM(pcilib_t *handle, const char *device) {
  1228. DIR *dir;
  1229. struct dirent *entry;
  1230. const char *pos;
  1231. char sysdir[256];
  1232. char fname[256];
  1233. char info[256];
  1234. char stmp[256];
  1235. size_t useid, i, n_uses = 1; // Use 0 is for others
  1236. kmem_use_info_t uses[MAX_USES];
  1237. memset(uses, 0, sizeof(uses));
  1238. pos = strrchr(device, '/');
  1239. if (pos) ++pos;
  1240. else pos = device;
  1241. snprintf(sysdir, 255, "/sys/class/fpga/%s", pos);
  1242. dir = opendir(sysdir);
  1243. if (!dir) Error("Can't open directory (%s)", sysdir);
  1244. while ((entry = readdir(dir)) != NULL) {
  1245. FILE *f;
  1246. unsigned long use = 0;
  1247. unsigned long size = 0;
  1248. unsigned long refs = 0;
  1249. unsigned long mode = 0;
  1250. unsigned long hwref = 0;
  1251. if (strncmp(entry->d_name, "kbuf", 4)) continue;
  1252. if (!isnumber(entry->d_name+4)) continue;
  1253. snprintf(fname, 255, "%s/%s", sysdir, entry->d_name);
  1254. f = fopen(fname, "r");
  1255. if (!f) Error("Can't access file (%s)", fname);
  1256. while(!feof(f)) {
  1257. fgets(info, 256, f);
  1258. if (!strncmp(info, "use:", 4)) use = strtoul(info+4, NULL, 16);
  1259. if (!strncmp(info, "size:", 5)) size = strtoul(info+5, NULL, 10);
  1260. if (!strncmp(info, "refs:", 5)) refs = strtoul(info+5, NULL, 10);
  1261. if (!strncmp(info, "mode:", 5)) mode = strtoul(info+5, NULL, 16);
  1262. if (!strncmp(info, "hw ref:", 7)) hwref = strtoul(info+7, NULL, 10);
  1263. }
  1264. fclose(f);
  1265. useid = FindUse(&n_uses, uses, use);
  1266. uses[useid].count++;
  1267. uses[useid].size += size;
  1268. if (refs) uses[useid].referenced = 1;
  1269. if (hwref) uses[useid].hw_lock = 1;
  1270. if (mode&KMEM_MODE_REUSABLE) uses[useid].reusable = 1;
  1271. if (mode&KMEM_MODE_PERSISTENT) uses[useid].persistent = 1;
  1272. if (mode&KMEM_MODE_COUNT) uses[useid].open = 1;
  1273. }
  1274. closedir(dir);
  1275. if ((n_uses == 1)&&(uses[0].count == 0)) {
  1276. printf("No kernel memory is allocated\n");
  1277. return 0;
  1278. }
  1279. printf("Use Type Count Total Size REF Mode \n");
  1280. printf("--------------------------------------------------------------------------------\n");
  1281. for (useid = 0; useid < n_uses; useid++) {
  1282. if (useid + 1 == n_uses) {
  1283. if (!uses[0].count) continue;
  1284. i = 0;
  1285. } else i = useid + 1;
  1286. printf("%08lx ", uses[i].use);
  1287. if (!i) printf("All Others ");
  1288. else if ((uses[i].use >> 16) == PCILIB_KMEM_USE_DMA_RING) printf("DMA%lu %s Ring ", uses[i].use&0x7F, ((uses[i].use&0x80)?"S2C":"C2S"));
  1289. else if ((uses[i].use >> 16) == PCILIB_KMEM_USE_DMA_PAGES) printf("DMA%lu %s Pages ", uses[i].use&0x7F, ((uses[i].use&0x80)?"S2C":"C2S"));
  1290. else printf (" ");
  1291. printf(" ");
  1292. printf("% 6lu", uses[i].count);
  1293. printf(" ");
  1294. printf("% 10s", PrintSize(stmp, uses[i].size));
  1295. printf(" ");
  1296. if (uses[i].referenced&&uses[i].hw_lock) printf("HW+SW");
  1297. else if (uses[i].referenced) printf(" SW");
  1298. else if (uses[i].hw_lock) printf("HW ");
  1299. else printf(" - ");
  1300. printf(" ");
  1301. if (uses[i].persistent) printf("Persistent");
  1302. else if (uses[i].open) printf("Open ");
  1303. else if (uses[i].reusable) printf("Reusable ");
  1304. else printf("Closed ");
  1305. printf("\n");
  1306. }
  1307. printf("--------------------------------------------------------------------------------\n");
  1308. printf("REF - Software/Hardware Reference, MODE - Reusable/Persistent/Open\n");
  1309. return 0;
  1310. }
  1311. int ReadKMEM(pcilib_t *handle, const char *device, pcilib_kmem_use_t use, size_t block, size_t max_size, FILE *o) {
  1312. void *data;
  1313. size_t size;
  1314. pcilib_kmem_handle_t *kbuf;
  1315. kbuf = pcilib_alloc_kernel_memory(handle, 0, block + 1, 0, 0, use, PCILIB_KMEM_FLAG_REUSE|PCILIB_KMEM_FLAG_TRY);
  1316. if (!kbuf) {
  1317. printf("The specified kernel buffer is not allocated\n");
  1318. return 0;
  1319. }
  1320. data = pcilib_kmem_get_block_ua(handle, kbuf, block);
  1321. if (data) {
  1322. size = pcilib_kmem_get_block_size(handle, kbuf, block);
  1323. if ((max_size)&&(size > max_size)) size = max_size;
  1324. fwrite(data, 1, size, o?o:stdout);
  1325. } else {
  1326. printf("The specified block is not existing\n");
  1327. }
  1328. pcilib_free_kernel_memory(handle, kbuf, KMEM_FLAG_REUSE);
  1329. return 0;
  1330. }
  1331. int FreeKMEM(pcilib_t *handle, const char *device, const char *use, int force) {
  1332. int err;
  1333. int i;
  1334. unsigned long useid;
  1335. pcilib_kmem_flags_t flags = PCILIB_KMEM_FLAG_HARDWARE|PCILIB_KMEM_FLAG_PERSISTENT|PCILIB_KMEM_FLAG_EXCLUSIVE;
  1336. if (force) flags |= PCILIB_KMEM_FLAG_FORCE; // this will ignore mmap locks as well.
  1337. if (!strcasecmp(use, "dma")) {
  1338. for (i = 0; i < PCILIB_MAX_DMA_ENGINES; i++) {
  1339. err = pcilib_clean_kernel_memory(handle, PCILIB_KMEM_USE(PCILIB_KMEM_USE_DMA_RING, i), flags);
  1340. if (err) Error("Error cleaning DMA%i C2S Ring buffer", i);
  1341. err = pcilib_clean_kernel_memory(handle, PCILIB_KMEM_USE(PCILIB_KMEM_USE_DMA_RING, 0x80|i), flags);
  1342. if (err) Error("Error cleaning DMA%i S2C Ring buffer", i);
  1343. err = pcilib_clean_kernel_memory(handle, PCILIB_KMEM_USE(PCILIB_KMEM_USE_DMA_PAGES, i), flags);
  1344. if (err) Error("Error cleaning DMA%i C2S Page buffers", i);
  1345. err = pcilib_clean_kernel_memory(handle, PCILIB_KMEM_USE(PCILIB_KMEM_USE_DMA_PAGES, 0x80|i), flags);
  1346. if (err) Error("Error cleaning DMA%i S2C Page buffers", i);
  1347. }
  1348. return 0;
  1349. }
  1350. if ((!isxnumber(use))||(sscanf(use, "%lx", &useid) != 1)) Error("Invalid use (%s) is specified", use);
  1351. err = pcilib_clean_kernel_memory(handle, useid, flags);
  1352. if (err) Error("Error cleaning kernel buffers for use (0x%lx)", useid);
  1353. return 0;
  1354. }
  1355. int ListDMA(pcilib_t *handle, const char *device, pcilib_model_description_t *model_info) {
  1356. int err;
  1357. DIR *dir;
  1358. struct dirent *entry;
  1359. const char *pos;
  1360. char sysdir[256];
  1361. char fname[256];
  1362. char info[256];
  1363. char stmp[256];
  1364. pcilib_dma_engine_t dmaid;
  1365. pcilib_dma_engine_status_t status;
  1366. pos = strrchr(device, '/');
  1367. if (pos) ++pos;
  1368. else pos = device;
  1369. snprintf(sysdir, 255, "/sys/class/fpga/%s", pos);
  1370. dir = opendir(sysdir);
  1371. if (!dir) Error("Can't open directory (%s)", sysdir);
  1372. printf("DMA Engine Status Total Size Buffer Ring (1st used - 1st free)\n");
  1373. printf("--------------------------------------------------------------------------------\n");
  1374. while ((entry = readdir(dir)) != NULL) {
  1375. FILE *f;
  1376. unsigned long use = 0;
  1377. unsigned long size = 0;
  1378. unsigned long refs = 0;
  1379. unsigned long mode = 0;
  1380. unsigned long hwref = 0;
  1381. if (strncmp(entry->d_name, "kbuf", 4)) continue;
  1382. if (!isnumber(entry->d_name+4)) continue;
  1383. snprintf(fname, 255, "%s/%s", sysdir, entry->d_name);
  1384. f = fopen(fname, "r");
  1385. if (!f) Error("Can't access file (%s)", fname);
  1386. while(!feof(f)) {
  1387. fgets(info, 256, f);
  1388. if (!strncmp(info, "use:", 4)) use = strtoul(info+4, NULL, 16);
  1389. if (!strncmp(info, "size:", 5)) size = strtoul(info+5, NULL, 10);
  1390. if (!strncmp(info, "refs:", 5)) refs = strtoul(info+5, NULL, 10);
  1391. if (!strncmp(info, "mode:", 5)) mode = strtoul(info+5, NULL, 16);
  1392. if (!strncmp(info, "hw ref:", 7)) hwref = strtoul(info+7, NULL, 10);
  1393. }
  1394. fclose(f);
  1395. if ((mode&(KMEM_MODE_REUSABLE|KMEM_MODE_PERSISTENT|KMEM_MODE_COUNT)) == 0) continue; // closed
  1396. if ((use >> 16) != PCILIB_KMEM_USE_DMA_RING) continue;
  1397. if (use&0x80) {
  1398. dmaid = pcilib_find_dma_by_addr(handle, PCILIB_DMA_TO_DEVICE, use&0x7F);
  1399. } else {
  1400. dmaid = pcilib_find_dma_by_addr(handle, PCILIB_DMA_FROM_DEVICE, use&0x7F);
  1401. }
  1402. if (dmaid == PCILIB_DMA_ENGINE_INVALID) continue;
  1403. printf("DMA%lu %s ", use&0x7F, (use&0x80)?"S2C":"C2S");
  1404. err = pcilib_start_dma(handle, dmaid, 0);
  1405. if (err) {
  1406. printf("-- Wrong state, start is failed\n");
  1407. continue;
  1408. }
  1409. err = pcilib_get_dma_status(handle, dmaid, &status, 0, NULL);
  1410. if (err) {
  1411. printf("-- Wrong state, failed to obtain status\n");
  1412. pcilib_stop_dma(handle, dmaid, 0);
  1413. continue;
  1414. }
  1415. pcilib_stop_dma(handle, dmaid, 0);
  1416. if (status.started) printf("S");
  1417. else printf(" ");
  1418. if (status.ring_head == status.ring_tail) printf(" ");
  1419. else printf("D");
  1420. printf(" ");
  1421. printf("% 10s", PrintSize(stmp, status.ring_size * status.buffer_size));
  1422. printf(" ");
  1423. printf("%zu - %zu (of %zu)", status.ring_tail, status.ring_head, status.ring_size);
  1424. printf("\n");
  1425. }
  1426. closedir(dir);
  1427. printf("--------------------------------------------------------------------------------\n");
  1428. printf("S - Started, D - Data in buffers\n");
  1429. return 0;
  1430. }
  1431. int ListBuffers(pcilib_t *handle, const char *device, pcilib_model_description_t *model_info, pcilib_dma_engine_addr_t dma, pcilib_dma_direction_t dma_direction) {
  1432. int err;
  1433. size_t i;
  1434. pcilib_dma_engine_t dmaid;
  1435. pcilib_dma_engine_status_t status;
  1436. pcilib_dma_buffer_status_t *buffer;
  1437. char stmp[256];
  1438. dmaid = pcilib_find_dma_by_addr(handle, dma_direction, dma);
  1439. if (dmaid == PCILIB_DMA_ENGINE_INVALID) Error("The specified DMA engine is not found");
  1440. err = pcilib_start_dma(handle, dmaid, 0);
  1441. if (err) Error("Error starting the specified DMA engine");
  1442. err = pcilib_get_dma_status(handle, dmaid, &status, 0, NULL);
  1443. if (err) Error("Failed to obtain status of the specified DMA engine");
  1444. buffer = (pcilib_dma_buffer_status_t*)malloc(status.ring_size*sizeof(pcilib_dma_buffer_status_t));
  1445. if (!buffer) Error("Failed to allocate memory for status buffer");
  1446. err = pcilib_get_dma_status(handle, dmaid, &status, status.ring_size, buffer);
  1447. if (err) Error("Failed to obtain extended status of the specified DMA engine");
  1448. printf("Buffer Status Total Size \n");
  1449. printf("--------------------------------------------------------------------------------\n");
  1450. for (i = 0; i < status.ring_size; i++) {
  1451. printf("%8zu ", i);
  1452. printf("%c%c %c%c ", buffer[i].used?'U':' ', buffer[i].error?'E':' ', buffer[i].first?'F':' ', buffer[i].last?'L':' ');
  1453. printf("% 10s", PrintSize(stmp, buffer[i].size));
  1454. printf("\n");
  1455. }
  1456. printf("--------------------------------------------------------------------------------\n");
  1457. printf("U - Used, E - Error, F - First block, L - Last Block\n");
  1458. free(buffer);
  1459. pcilib_stop_dma(handle, dmaid, 0);
  1460. return 0;
  1461. }
  1462. int ReadBuffer(pcilib_t *handle, const char *device, pcilib_model_description_t *model_info, pcilib_dma_engine_addr_t dma, pcilib_dma_direction_t dma_direction, size_t block, FILE *o) {
  1463. int err;
  1464. pcilib_dma_engine_t dmaid;
  1465. pcilib_dma_engine_status_t status;
  1466. pcilib_dma_buffer_status_t *buffer;
  1467. size_t size;
  1468. dmaid = pcilib_find_dma_by_addr(handle, dma_direction, dma);
  1469. if (dmaid == PCILIB_DMA_ENGINE_INVALID) Error("The specified DMA engine is not found");
  1470. err = pcilib_start_dma(handle, dmaid, 0);
  1471. if (err) Error("Error starting the specified DMA engine");
  1472. err = pcilib_get_dma_status(handle, dmaid, &status, 0, NULL);
  1473. if (err) Error("Failed to obtain status of the specified DMA engine");
  1474. buffer = (pcilib_dma_buffer_status_t*)malloc(status.ring_size*sizeof(pcilib_dma_buffer_status_t));
  1475. if (!buffer) Error("Failed to allocate memory for status buffer");
  1476. err = pcilib_get_dma_status(handle, dmaid, &status, status.ring_size, buffer);
  1477. if (err) Error("Failed to obtain extended status of the specified DMA engine");
  1478. if (block == (size_t)-1) {
  1479. // get current
  1480. }
  1481. size = buffer[block].size;
  1482. free(buffer);
  1483. pcilib_stop_dma(handle, dmaid, 0);
  1484. // printf("%i %i\n", dma, buffer);
  1485. // printf("%lx\n", ((dma&0x7F)|((dma_direction == PCILIB_DMA_TO_DEVICE)?0x80:0x00))|(PCILIB_KMEM_USE_DMA_PAGES<<16));
  1486. return ReadKMEM(handle, device, ((dma&0x7F)|((dma_direction == PCILIB_DMA_TO_DEVICE)?0x80:0x00))|(PCILIB_KMEM_USE_DMA_PAGES<<16), block, size, o);
  1487. }
  1488. int WaitIRQ(pcilib_t *handle, pcilib_model_description_t *model_info, pcilib_irq_hw_source_t irq_source, pcilib_timeout_t timeout) {
  1489. int err;
  1490. size_t count;
  1491. err = pcilib_enable_irq(handle, PCILIB_EVENT_IRQ, 0);
  1492. if (err) Error("Error enabling IRQs");
  1493. err = pcilib_wait_irq(handle, irq_source, timeout, &count);
  1494. if (err) {
  1495. if (err == PCILIB_ERROR_TIMEOUT) Error("Timeout waiting for IRQ");
  1496. else Error("Error waiting for IRQ");
  1497. }
  1498. return 0;
  1499. }
  1500. int main(int argc, char **argv) {
  1501. int i;
  1502. long itmp;
  1503. unsigned long utmp;
  1504. size_t ztmp;
  1505. unsigned char c;
  1506. const char *stmp;
  1507. const char *num_offset;
  1508. int details = 0;
  1509. int quiete = 0;
  1510. int force = 0;
  1511. pcilib_model_t model = PCILIB_MODEL_DETECT;
  1512. pcilib_model_description_t *model_info;
  1513. MODE mode = MODE_INVALID;
  1514. GRAB_MODE grab_mode = 0;
  1515. size_t trigger_time = 0;
  1516. size_t run_time = 0;
  1517. size_t buffer = 0;
  1518. FORMAT format = FORMAT_RAW;
  1519. PARTITION partition = PARTITION_UNKNOWN;
  1520. FLAGS flags = 0;
  1521. const char *type = NULL;
  1522. ACCESS_MODE amode = ACCESS_BAR;
  1523. const char *fpga_device = DEFAULT_FPGA_DEVICE;
  1524. pcilib_bar_t bar = PCILIB_BAR_DETECT;
  1525. const char *addr = NULL;
  1526. const char *reg = NULL;
  1527. const char *bank = NULL;
  1528. char **data = NULL;
  1529. const char *event = NULL;
  1530. const char *data_type = NULL;
  1531. const char *dma_channel = NULL;
  1532. const char *use = NULL;
  1533. pcilib_kmem_use_t use_id = 0;
  1534. size_t block = 0;
  1535. pcilib_irq_hw_source_t irq_source = PCILIB_IRQ_SOURCE_DEFAULT;
  1536. pcilib_dma_direction_t dma_direction = PCILIB_DMA_BIDIRECTIONAL;
  1537. pcilib_dma_engine_addr_t dma = PCILIB_DMA_ENGINE_ADDR_INVALID;
  1538. long addr_shift = 0;
  1539. uintptr_t start = -1;
  1540. size_t size = 1;
  1541. access_t access = 4;
  1542. // int skip = 0;
  1543. int endianess = 0;
  1544. size_t timeout = 0;
  1545. const char *output = NULL;
  1546. FILE *ofile = NULL;
  1547. size_t iterations = BENCHMARK_ITERATIONS;
  1548. pcilib_t *handle;
  1549. int size_set = 0;
  1550. int timeout_set = 0;
  1551. int run_time_set = 0;
  1552. while ((c = getopt_long(argc, argv, "hqilr::w::g::d:m:t:b:a:s:e:o:", long_options, NULL)) != (unsigned char)-1) {
  1553. extern int optind;
  1554. switch (c) {
  1555. case OPT_HELP:
  1556. Usage(argc, argv, NULL);
  1557. break;
  1558. case OPT_INFO:
  1559. if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1560. mode = MODE_INFO;
  1561. break;
  1562. case OPT_LIST:
  1563. if (mode == MODE_LIST) details++;
  1564. else if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1565. mode = MODE_LIST;
  1566. break;
  1567. case OPT_RESET:
  1568. if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1569. mode = MODE_RESET;
  1570. break;
  1571. case OPT_BENCHMARK:
  1572. if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1573. mode = MODE_BENCHMARK;
  1574. if (optarg) addr = optarg;
  1575. else if ((optind < argc)&&(argv[optind][0] != '-')) addr = argv[optind++];
  1576. break;
  1577. case OPT_READ:
  1578. if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1579. mode = MODE_READ;
  1580. if (optarg) addr = optarg;
  1581. else if ((optind < argc)&&(argv[optind][0] != '-')) addr = argv[optind++];
  1582. break;
  1583. case OPT_WRITE:
  1584. if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1585. mode = MODE_WRITE;
  1586. if (optarg) addr = optarg;
  1587. else if ((optind < argc)&&(argv[optind][0] != '-')) addr = argv[optind++];
  1588. break;
  1589. case OPT_GRAB:
  1590. if ((mode != MODE_INVALID)&&((mode != MODE_GRAB)||(grab_mode&GRAB_MODE_GRAB))) Usage(argc, argv, "Multiple operations are not supported");
  1591. mode = MODE_GRAB;
  1592. grab_mode |= GRAB_MODE_GRAB;
  1593. stmp = NULL;
  1594. if (optarg) stmp = optarg;
  1595. else if ((optind < argc)&&(argv[optind][0] != '-')) stmp = argv[optind++];
  1596. if (stmp) {
  1597. if ((event)&&(strcasecmp(stmp,event))) Usage(argc, argv, "Redefinition of considered event");
  1598. event = stmp;
  1599. }
  1600. break;
  1601. case OPT_TRIGGER:
  1602. if ((mode != MODE_INVALID)&&((mode != MODE_GRAB)||(grab_mode&GRAB_MODE_TRIGGER))) Usage(argc, argv, "Multiple operations are not supported");
  1603. mode = MODE_GRAB;
  1604. grab_mode |= GRAB_MODE_TRIGGER;
  1605. stmp = NULL;
  1606. if (optarg) stmp = optarg;
  1607. else if ((optind < argc)&&(argv[optind][0] != '-')) stmp = argv[optind++];
  1608. if (stmp) {
  1609. if ((event)&&(strcasecmp(stmp,event))) Usage(argc, argv, "Redefinition of considered event");
  1610. event = stmp;
  1611. }
  1612. break;
  1613. case OPT_LIST_DMA:
  1614. if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1615. mode = MODE_LIST_DMA;
  1616. break;
  1617. case OPT_LIST_DMA_BUFFERS:
  1618. if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1619. mode = MODE_LIST_DMA_BUFFERS;
  1620. dma_channel = optarg;
  1621. break;
  1622. case OPT_READ_DMA_BUFFER:
  1623. if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1624. mode = MODE_READ_DMA_BUFFER;
  1625. num_offset = strchr(optarg, ':');
  1626. if (num_offset) {
  1627. if (sscanf(num_offset + 1, "%zu", &block) != 1)
  1628. Usage(argc, argv, "Invalid buffer is specified (%s)", num_offset + 1);
  1629. *(char*)num_offset = 0;
  1630. } else block = (size_t)-1;
  1631. dma_channel = optarg;
  1632. break;
  1633. case OPT_START_DMA:
  1634. if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1635. mode = MODE_START_DMA;
  1636. if (optarg) dma_channel = optarg;
  1637. else if ((optind < argc)&&(argv[optind][0] != '-')) dma_channel = argv[optind++];
  1638. break;
  1639. case OPT_STOP_DMA:
  1640. if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1641. mode = MODE_STOP_DMA;
  1642. if (optarg) dma_channel = optarg;
  1643. else if ((optind < argc)&&(argv[optind][0] != '-')) dma_channel = argv[optind++];
  1644. break;
  1645. case OPT_WAIT_IRQ:
  1646. if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1647. mode = MODE_WAIT_IRQ;
  1648. if (optarg) num_offset = optarg;
  1649. else if ((optind < argc)&&(argv[optind][0] != '-')) num_offset = argv[optind++];
  1650. else num_offset = NULL;
  1651. if (num_offset) {
  1652. if ((!isnumber(num_offset))||(sscanf(num_offset, "%li", &itmp) != 1))
  1653. Usage(argc, argv, "Invalid IRQ source is specified (%s)", num_offset);
  1654. irq_source = itmp;
  1655. }
  1656. break;
  1657. case OPT_LIST_KMEM:
  1658. if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1659. mode = MODE_LIST_KMEM;
  1660. break;
  1661. case OPT_READ_KMEM:
  1662. if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1663. mode = MODE_READ_KMEM;
  1664. num_offset = strchr(optarg, ':');
  1665. if (num_offset) {
  1666. if (sscanf(num_offset + 1, "%zu", &block) != 1)
  1667. Usage(argc, argv, "Invalid block number is specified (%s)", num_offset + 1);
  1668. *(char*)num_offset = 0;
  1669. }
  1670. if (sscanf(optarg, "%lx", &utmp) != 1)
  1671. Usage(argc, argv, "Invalid USE number is specified (%s)", optarg);
  1672. if (!utmp)
  1673. Usage(argc, argv, "Can't read buffer with the unspecific use (use number is 0)");
  1674. use_id = utmp;
  1675. break;
  1676. case OPT_FREE_KMEM:
  1677. if (mode != MODE_INVALID) Usage(argc, argv, "Multiple operations are not supported");
  1678. mode = MODE_FREE_KMEM;
  1679. if (optarg) use = optarg;
  1680. else if ((optind < argc)&&(argv[optind][0] != '-')) use = argv[optind++];
  1681. break;
  1682. case OPT_DEVICE:
  1683. fpga_device = optarg;
  1684. break;
  1685. case OPT_MODEL:
  1686. if (!strcasecmp(optarg, "pci")) model = PCILIB_MODEL_PCI;
  1687. else if (!strcasecmp(optarg, "ipecamera")) model = PCILIB_MODEL_IPECAMERA;
  1688. else Usage(argc, argv, "Invalid memory model (%s) is specified", optarg);
  1689. break;
  1690. case OPT_BAR:
  1691. bank = optarg;
  1692. // if ((sscanf(optarg,"%li", &itmp) != 1)||(itmp < 0)||(itmp >= PCILIB_MAX_BANKS)) Usage(argc, argv, "Invalid data bank (%s) is specified", optarg);
  1693. // else bar = itmp;
  1694. break;
  1695. case OPT_ACCESS:
  1696. if (!strncasecmp(optarg, "fifo", 4)) {
  1697. type = "fifo";
  1698. num_offset = optarg + 4;
  1699. amode = ACCESS_FIFO;
  1700. } else if (!strncasecmp(optarg, "dma", 3)) {
  1701. type = "dma";
  1702. num_offset = optarg + 3;
  1703. amode = ACCESS_DMA;
  1704. } else if (!strncasecmp(optarg, "bar", 3)) {
  1705. type = "plain";
  1706. num_offset = optarg + 3;
  1707. amode = ACCESS_BAR;
  1708. } else if (!strncasecmp(optarg, "plain", 5)) {
  1709. type = "plain";
  1710. num_offset = optarg + 5;
  1711. amode = ACCESS_BAR;
  1712. } else {
  1713. num_offset = optarg;
  1714. }
  1715. if (*num_offset) {
  1716. if ((!isnumber(num_offset))||(sscanf(num_offset, "%li", &itmp) != 1))
  1717. Usage(argc, argv, "Invalid access type (%s) is specified", optarg);
  1718. switch (itmp) {
  1719. case 8: access = 1; break;
  1720. case 16: access = 2; break;
  1721. case 32: access = 4; break;
  1722. case 64: access = 8; break;
  1723. default: Usage(argc, argv, "Invalid data width (%s) is specified", num_offset);
  1724. }
  1725. }
  1726. break;
  1727. case OPT_SIZE:
  1728. if ((!isnumber(optarg))||(sscanf(optarg, "%zu", &size) != 1)) {
  1729. if (strcasecmp(optarg, "unlimited"))
  1730. Usage(argc, argv, "Invalid size is specified (%s)", optarg);
  1731. else
  1732. size = 0;//(size_t)-1;
  1733. }
  1734. size_set = 1;
  1735. break;
  1736. case OPT_ENDIANESS:
  1737. if ((*optarg == 'b')||(*optarg == 'B')) {
  1738. if (ntohs(1) == 1) endianess = 0;
  1739. else endianess = 1;
  1740. } else if ((*optarg == 'l')||(*optarg == 'L')) {
  1741. if (ntohs(1) == 1) endianess = 1;
  1742. else endianess = 0;
  1743. } else Usage(argc, argv, "Invalid endianess is specified (%s)", optarg);
  1744. break;
  1745. case OPT_TIMEOUT:
  1746. if ((!isnumber(optarg))||(sscanf(optarg, "%zu", &timeout) != 1)) {
  1747. if (strcasecmp(optarg, "unlimited"))
  1748. Usage(argc, argv, "Invalid timeout is specified (%s)", optarg);
  1749. else
  1750. timeout = PCILIB_TIMEOUT_INFINITE;
  1751. }
  1752. timeout_set = 1;
  1753. break;
  1754. case OPT_OUTPUT:
  1755. output = optarg;
  1756. break;
  1757. case OPT_ITERATIONS:
  1758. if ((!isnumber(optarg))||(sscanf(optarg, "%zu", &iterations) != 1))
  1759. Usage(argc, argv, "Invalid number of iterations is specified (%s)", optarg);
  1760. break;
  1761. case OPT_EVENT:
  1762. event = optarg;
  1763. break;
  1764. case OPT_DATA_TYPE:
  1765. data_type = optarg;
  1766. break;
  1767. case OPT_RUN_TIME:
  1768. if ((!isnumber(optarg))||(sscanf(optarg, "%zu", &run_time) != 1)) {
  1769. if (strcasecmp(optarg, "unlimited"))
  1770. Usage(argc, argv, "Invalid run-time is specified (%s)", optarg);
  1771. else
  1772. run_time = 0;
  1773. }
  1774. run_time_set = 1;
  1775. break;
  1776. case OPT_TRIGGER_TIME:
  1777. if ((!isnumber(optarg))||(sscanf(optarg, "%zu", &trigger_time) != 1))
  1778. Usage(argc, argv, "Invalid trigger-time is specified (%s)", optarg);
  1779. break;
  1780. case OPT_TRIGGER_RATE:
  1781. if ((!isnumber(optarg))||(sscanf(optarg, "%zu", &ztmp) != 1))
  1782. Usage(argc, argv, "Invalid trigger-rate is specified (%s)", optarg);
  1783. trigger_time = (1000000 / ztmp) + ((1000000 % ztmp)?1:0);
  1784. break;
  1785. case OPT_BUFFER:
  1786. if (optarg) num_offset = optarg;
  1787. else if ((optind < argc)&&(argv[optind][0] != '-')) num_offset = argv[optind++];
  1788. else num_offset = NULL;
  1789. if (num_offset) {
  1790. if ((!isnumber(num_offset))||(sscanf(num_offset, "%zu", &buffer) != 1))
  1791. Usage(argc, argv, "Invalid buffer size is specified (%s)", num_offset);
  1792. buffer *= 1024 * 1024;
  1793. } else {
  1794. buffer = get_free_memory();
  1795. if (buffer < 256) Error("Not enough free memory (%lz MB) for buffering", buffer / 1024 / 1024);
  1796. buffer -= 128 + buffer/16;
  1797. }
  1798. break;
  1799. case OPT_FORMAT:
  1800. if (!strcasecmp(optarg, "add_header")) format = FORMAT_HEADER;
  1801. else if (!strcasecmp(optarg, "ringfs")) format = FORMAT_RINGFS;
  1802. else if (strcasecmp(optarg, "raw")) Error("Invalid format (%s) is specified", optarg);
  1803. break;
  1804. case OPT_QUIETE:
  1805. quiete = 1;
  1806. break;
  1807. case OPT_FORCE:
  1808. force = 1;
  1809. break;
  1810. case OPT_MULTIPACKET:
  1811. flags |= FLAG_MULTIPACKET;
  1812. break;
  1813. case OPT_WAIT:
  1814. flags |= FLAG_WAIT;
  1815. break;
  1816. default:
  1817. Usage(argc, argv, "Unknown option (%s) with argument (%s)", optarg?argv[optind-2]:argv[optind-1], optarg?optarg:"(null)");
  1818. }
  1819. }
  1820. if (mode == MODE_INVALID) {
  1821. if (argc > 1) Usage(argc, argv, "Operation is not specified");
  1822. else Usage(argc, argv, NULL);
  1823. }
  1824. pcilib_set_error_handler(&Error, quiete?Silence:NULL);
  1825. handle = pcilib_open(fpga_device, model);
  1826. if (handle < 0) Error("Failed to open FPGA device: %s", fpga_device);
  1827. model = pcilib_get_model(handle);
  1828. model_info = pcilib_get_model_description(handle);
  1829. switch (mode) {
  1830. case MODE_WRITE:
  1831. if (!addr) Usage(argc, argv, "The address is not specified");
  1832. if (((argc - optind) == 1)&&(*argv[optind] == '*')) {
  1833. int vallen = strlen(argv[optind]);
  1834. if (vallen > 1) {
  1835. data = (char**)malloc(size * (vallen + sizeof(char*)));
  1836. if (!data) Error("Error allocating memory for data array");
  1837. for (i = 0; i < size; i++) {
  1838. data[i] = ((char*)data) + size * sizeof(char*) + i * vallen;
  1839. strcpy(data[i], argv[optind] + 1);
  1840. }
  1841. } else {
  1842. data = (char**)malloc(size * (9 + sizeof(char*)));
  1843. if (!data) Error("Error allocating memory for data array");
  1844. for (i = 0; i < size; i++) {
  1845. data[i] = ((char*)data) + size * sizeof(char*) + i * 9;
  1846. sprintf(data[i], "%x", i);
  1847. }
  1848. }
  1849. } else if ((argc - optind) == size) data = argv + optind;
  1850. else Usage(argc, argv, "The %i data values is specified, but %i required", argc - optind, size);
  1851. break;
  1852. case MODE_READ:
  1853. if (!addr) {
  1854. if (model == PCILIB_MODEL_PCI) {
  1855. Usage(argc, argv, "The address is not specified");
  1856. } else ++mode;
  1857. }
  1858. break;
  1859. case MODE_START_DMA:
  1860. case MODE_STOP_DMA:
  1861. case MODE_LIST_DMA_BUFFERS:
  1862. case MODE_READ_DMA_BUFFER:
  1863. if ((dma_channel)&&(*dma_channel)) {
  1864. itmp = strlen(dma_channel) - 1;
  1865. if (dma_channel[itmp] == 'r') dma_direction = PCILIB_DMA_FROM_DEVICE;
  1866. else if (dma_channel[itmp] == 'w') dma_direction = PCILIB_DMA_TO_DEVICE;
  1867. if (dma_direction != PCILIB_DMA_BIDIRECTIONAL) itmp--;
  1868. if (strncmp(dma_channel, "dma", 3)) num_offset = dma_channel;
  1869. else {
  1870. num_offset = dma_channel + 3;
  1871. itmp -= 3;
  1872. }
  1873. if (bank) {
  1874. if (strncmp(num_offset, bank, itmp)) Usage(argc, argv, "Conflicting DMA channels are specified in mode parameter (%s) and bank parameter (%s)", dma_channel, bank);
  1875. }
  1876. if (!isnumber_n(num_offset, itmp))
  1877. Usage(argc, argv, "Invalid DMA channel (%s) is specified", dma_channel);
  1878. dma = atoi(num_offset);
  1879. }
  1880. break;
  1881. default:
  1882. if (argc > optind) Usage(argc, argv, "Invalid non-option parameters are supplied");
  1883. }
  1884. if (addr) {
  1885. if ((!strncmp(addr, "dma", 3))&&((addr[3]==0)||isnumber(addr+3))) {
  1886. if ((type)&&(amode != ACCESS_DMA)) Usage(argc, argv, "Conflicting access modes, the DMA read is requested, but access type is (%s)", type);
  1887. if (bank) {
  1888. if ((addr[3] != 0)&&(strcmp(addr + 3, bank))) Usage(argc, argv, "Conflicting DMA channels are specified in read parameter (%s) and bank parameter (%s)", addr + 3, bank);
  1889. } else {
  1890. if (addr[3] == 0) Usage(argc, argv, "The DMA channel is not specified");
  1891. }
  1892. dma = atoi(addr + 3);
  1893. amode = ACCESS_DMA;
  1894. } else if ((!strncmp(addr, "bar", 3))&&((addr[3]==0)||isnumber(addr+3))) {
  1895. if ((type)&&(amode != ACCESS_BAR)) Usage(argc, argv, "Conflicting access modes, the plain PCI read is requested, but access type is (%s)", type);
  1896. if ((addr[3] != 0)&&(strcmp(addr + 3, bank))) Usage(argc, argv, "Conflicting PCI bars are specified in read parameter (%s) and bank parameter (%s)", addr + 3, bank);
  1897. bar = atoi(addr + 3);
  1898. amode = ACCESS_BAR;
  1899. } else if ((isxnumber(addr))&&(sscanf(addr, "%lx", &start) == 1)) {
  1900. // check if the address in the register range
  1901. pcilib_register_range_t *ranges = model_info->ranges;
  1902. if (ranges) {
  1903. for (i = 0; ranges[i].start != ranges[i].end; i++)
  1904. if ((start >= ranges[i].start)&&(start <= ranges[i].end)) break;
  1905. // register access in plain mode
  1906. if (ranges[i].start != ranges[i].end) {
  1907. pcilib_register_bank_t regbank = pcilib_find_bank_by_addr(handle, ranges[i].bank);
  1908. if (regbank == PCILIB_REGISTER_BANK_INVALID) Error("Configuration error: register bank specified in the address range is not found");
  1909. bank = model_info->banks[regbank].name;
  1910. start += ranges[i].addr_shift;
  1911. addr_shift = ranges[i].addr_shift;
  1912. ++mode;
  1913. }
  1914. }
  1915. } else {
  1916. if (pcilib_find_register(handle, bank, addr) == PCILIB_REGISTER_INVALID) {
  1917. Usage(argc, argv, "Invalid address (%s) is specified", addr);
  1918. } else {
  1919. reg = addr;
  1920. ++mode;
  1921. }
  1922. }
  1923. }
  1924. if (mode == MODE_GRAB) {
  1925. if (output) {
  1926. char fsname[128];
  1927. if (!get_file_fs(output, 127, fsname)) {
  1928. if (!strcmp(fsname, "ext4")) partition = PARTITION_EXT4;
  1929. else if (!strcmp(fsname, "raw")) partition = PARTITION_RAW;
  1930. }
  1931. } else {
  1932. output = "/dev/null";
  1933. partition = PARTITION_NULL;
  1934. }
  1935. if (!timeout_set) {
  1936. if (run_time) timeout = PCILIB_TIMEOUT_INFINITE;
  1937. else timeout = PCILIB_EVENT_TIMEOUT;
  1938. }
  1939. }
  1940. if (mode != MODE_GRAB) {
  1941. if (size == (size_t)-1)
  1942. Usage(argc, argv, "Unlimited size is not supported in selected operation mode");
  1943. }
  1944. if ((bank)&&(amode == ACCESS_DMA)) {
  1945. if ((!isnumber(bank))||(sscanf(bank,"%li", &itmp) != 1)||(itmp < 0))
  1946. Usage(argc, argv, "Invalid DMA channel (%s) is specified", bank);
  1947. else dma = itmp;
  1948. } else if (bank) {
  1949. switch (mode) {
  1950. case MODE_BENCHMARK:
  1951. case MODE_READ:
  1952. case MODE_WRITE:
  1953. if ((!isnumber(bank))||(sscanf(bank,"%li", &itmp) != 1)||(itmp < 0)||(itmp >= PCILIB_MAX_BANKS))
  1954. Usage(argc, argv, "Invalid data bank (%s) is specified", bank);
  1955. else bar = itmp;
  1956. break;
  1957. default:
  1958. if (pcilib_find_bank(handle, bank) == PCILIB_REGISTER_BANK_INVALID)
  1959. Usage(argc, argv, "Invalid data bank (%s) is specified", bank);
  1960. }
  1961. }
  1962. if (output) {
  1963. ofile = fopen(output, "a+");
  1964. if (!ofile) {
  1965. Error("Failed to open file \"%s\"", output);
  1966. }
  1967. }
  1968. switch (mode) {
  1969. case MODE_INFO:
  1970. Info(handle, model_info);
  1971. break;
  1972. case MODE_LIST:
  1973. List(handle, model_info, bank, details);
  1974. break;
  1975. case MODE_BENCHMARK:
  1976. Benchmark(handle, amode, dma, bar, start, size_set?size:0, access, iterations);
  1977. break;
  1978. case MODE_READ:
  1979. if (amode == ACCESS_DMA) {
  1980. ReadData(handle, amode, flags, dma, bar, start, size_set?size:0, access, endianess, timeout_set?timeout:(size_t)-1, ofile);
  1981. } else if (addr) {
  1982. ReadData(handle, amode, flags, dma, bar, start, size, access, endianess, (size_t)-1, ofile);
  1983. } else {
  1984. Error("Address to read is not specified");
  1985. }
  1986. break;
  1987. case MODE_READ_REGISTER:
  1988. if ((reg)||(!addr)) ReadRegister(handle, model_info, bank, reg);
  1989. else ReadRegisterRange(handle, model_info, bank, start, addr_shift, size, ofile);
  1990. break;
  1991. case MODE_WRITE:
  1992. WriteData(handle, amode, dma, bar, start, size, access, endianess, data);
  1993. break;
  1994. case MODE_WRITE_REGISTER:
  1995. if (reg) WriteRegister(handle, model_info, bank, reg, data);
  1996. else WriteRegisterRange(handle, model_info, bank, start, addr_shift, size, data);
  1997. break;
  1998. case MODE_RESET:
  1999. pcilib_reset(handle);
  2000. break;
  2001. case MODE_GRAB:
  2002. TriggerAndGrab(handle, grab_mode, event, data_type, size, run_time, trigger_time, timeout, partition, format, buffer, ofile);
  2003. break;
  2004. case MODE_LIST_DMA:
  2005. ListDMA(handle, fpga_device, model_info);
  2006. break;
  2007. case MODE_LIST_DMA_BUFFERS:
  2008. ListBuffers(handle, fpga_device, model_info, dma, dma_direction);
  2009. break;
  2010. case MODE_READ_DMA_BUFFER:
  2011. ReadBuffer(handle, fpga_device, model_info, dma, dma_direction, block, ofile);
  2012. break;
  2013. case MODE_START_DMA:
  2014. StartStopDMA(handle, model_info, dma, dma_direction, 1);
  2015. break;
  2016. case MODE_STOP_DMA:
  2017. StartStopDMA(handle, model_info, dma, dma_direction, 0);
  2018. break;
  2019. case MODE_WAIT_IRQ:
  2020. WaitIRQ(handle, model_info, irq_source, timeout);
  2021. break;
  2022. case MODE_LIST_KMEM:
  2023. ListKMEM(handle, fpga_device);
  2024. break;
  2025. case MODE_READ_KMEM:
  2026. ReadKMEM(handle, fpga_device, use_id, block, 0, ofile);
  2027. break;
  2028. case MODE_FREE_KMEM:
  2029. FreeKMEM(handle, fpga_device, use, force);
  2030. break;
  2031. case MODE_INVALID:
  2032. break;
  2033. }
  2034. if (ofile) fclose(ofile);
  2035. pcilib_close(handle);
  2036. if (data != argv + optind) free(data);
  2037. }