Use defines

ddrio.c

@@ -9,6 +9,8 @@
 #include <pcilib/bar.h>
 #include <pcilib/kmem.h>
 
+#include "hf-interface.h"
+
 /* this should actually come from the distributed pcitool sources */
 #include "pciDriver.h"
 
@@ -134,14 +136,18 @@ write_to_ddr (pcilib_t *pci, volatile void *bar, Options *opts)
     }
 
     /* reset DDR and FIFOs */
-    WR32_sleep (0x9040, 0x1000F);
+    WR32_sleep (HF_REG_CONTROL,
+                HF_CONTROL_RESET |
+                HF_CONTROL_SOFT_RESET |
+                0x3 | /* what does this even mean? */
+                HF_CONTROL_SOURCE_DCG);
 
     /* write only in DDR mode, disable read */
-    WR32_sleep (0x9040, 0x10000);
+    WR32_sleep (HF_REG_CONTROL, HF_CONTROL_SOURCE_DCG);
 
     /* reset DMA */
-    WR32_sleep (0x0, 1);
-    WR32_sleep (0x0, 0);
+    WR32_sleep (HF_REG_BASE, HF_BASE_RESET);
+    WR32_sleep (HF_REG_BASE, !HF_BASE_RESET);
 
     switch (opts->copy) {
         case COPY_MEMCPY:
@@ -198,16 +204,19 @@ read_from_ddr (pcilib_t *pci, volatile void *bar, Options *opts)
     bus_addr = pcilib_kmem_get_block_ba (pci, kmem, 0);
 
     /* enable multi-read from DDR */
-    WR32_sleep (0x9040, 0x10C00);
+    WR32_sleep (HF_REG_CONTROL,
+                HF_CONTROL_ENABLE_READ |
+                HF_CONTROL_ENABLE_MULTI_READ |
+                HF_CONTROL_SOURCE_DCG);
 
     /* DMA config */
-    WR32_sleep (0x10, 0x20);
-    WR32_sleep (0x0C, 0x20);
-    WR32_sleep (0x60, 1);
+    WR32_sleep (HF_REG_NUM_PACKETS, 0x20);
+    WR32_sleep (HF_REG_PACKET_LENGTH, 0x20);
+    WR32_sleep (HF_REG_UPDATE_THRESHOLD, 1);
 
     while (size >= mem_size) {
         /* set write addr */
-        WR64 (0x50, bus_addr);
+        WR64 (HF_REG_DESCRIPTOR_ADDRESS, bus_addr);
 
         /* start DMA */
         if (!started) {
@@ -222,20 +231,20 @@ read_from_ddr (pcilib_t *pci, volatile void *bar, Options *opts)
     }
 
     if (size > 0) {
-        WR64_sleep (0x50, bus_addr);
-        WR32_sleep (0x04, 1);
+        WR64_sleep (HF_REG_DESCRIPTOR_ADDRESS, bus_addr);
+        WR32_sleep (HF_REG_DMA, HF_DMA_START);
 
         usleep (100);
         fwrite (mem, 1, size, fp);
     }
 
-    WR32_sleep (0x04, 0);
+    WR32_sleep (HF_REG_DMA, HF_DMA_STOP);
     fclose (fp);
 
     pcilib_free_kernel_memory (pci, kmem, KMEM_DEFAULT_FLAGS);
 }
 
-int 
+int
 main (int argc, char const* argv[])
 {
     static const char *DEVICE = "/dev/fpga0";
@@ -257,10 +266,10 @@ main (int argc, char const* argv[])
     bar = pcilib_resolve_bar_address (pci, PCILIB_BAR0, 0);
 
     /* reset dbg tx */
-    WR32_sleep (0x9344, 1);
-    WR32_sleep (0x9344, 0);
-    WR32_sleep (0x93A4, 1);
-    WR32_sleep (0x93A4, 0);
+    WR32_sleep (HF_REG_DEBUG_REQUESTER_RESET, 1);
+    WR32_sleep (HF_REG_DEBUG_REQUESTER_RESET, 0);
+    WR32_sleep (HF_REG_DEBUG_COMPLETER_RESET, 1);
+    WR32_sleep (HF_REG_DEBUG_COMPLETER_RESET, 0);
 
     if (opts.input != NULL)
         write_to_ddr (pci, bar, &opts);

hf-interface.h

@@ -0,0 +1,54 @@
+#ifndef HF_INTERFACE_H
+#define HF_INTERFACE_H
+
+/* internal registers */
+
+#define HF_REG_BASE                     0x00
+#define HF_REG_DMA                      0x04
+#define HF_REG_NUM_PACKETS              0x10
+#define HF_REG_PERF_COUNTER             0x28
+#define HF_REG_PACKET_LENGTH            0x0C
+#define HF_REG_DESCRIPTOR_ADDRESS       0x50
+#define HF_REG_UPDATE_ADDRESS           0x58
+#define HF_REG_UPDATE_THRESHOLD         0x60
+
+/* internal register masks and values */
+
+#define HF_BASE_RESET                   0x00000001
+#define HF_BASE_VERSION                 0x0000FF00
+#define HF_BASE_DATAPATH_WIDTH          0x000F0000
+#define HF_BASE_FPGA_FAMILY             0xFF000000
+#define HF_DMA_START                    0x1
+#define HF_DMA_STOP                     0x0
+
+
+/* user registers */
+
+#define HF_REG_DCG                      0x9000
+#define HF_REG_DCG_FIXED_PATTERN        0x9004
+#define HF_REG_DCG_FIXED_PATTERN_1ST    0x9008
+#define HF_REG_VERSION                  0x9020
+#define HF_REG_CONTROL                  0x9040
+#define HF_REG_LATENCY                  0x9044
+#define HF_REG_DFG_NUM_ROWS             0x9168
+#define HF_REG_DFG_NUM_FRAMES           0x9170
+#define HF_REG_DEBUG_REQUESTER_RESET    0x9344
+#define HF_REG_DEBUG_COMPLETER_RESET    0x93A4
+
+/* user register masks and values */
+
+#define HF_DCG_START                    0x00000001
+#define HF_DCG_RESET                    0x00000010
+#define HF_DCG_ENABLE_FIXED_PATTERN     0x00000100
+#define HF_CONTROL_RESET                0x00000004
+#define HF_CONTROL_SOFT_RESET           0x00000008
+#define HF_CONTROL_ENABLE_READ          0x00000400
+#define HF_CONTROL_ENABLE_MULTI_READ    0x00000800
+#define HF_CONTROL_GLOBAL_COUNTER_RESET 0x00008000
+#define HF_CONTROL_SOURCE_MASK          0x000F0000
+#define HF_CONTROL_SOURCE_DCG           0x00010000
+#define HF_CONTROL_SOURCE_RX_FIFO       0x00020000
+#define HF_CONTROL_SOURCE_DFG           0x00040000
+#define HF_CONTROL_SOURCE_DCG_NO_DDR    0x00080000
+
+#endif