|
@@ -135,19 +135,19 @@ write_to_ddr (pcilib_t *pci, volatile void *bar, Options *opts)
|
|
|
read_size, size);
|
|
|
}
|
|
|
|
|
|
+ /* reset DMA */
|
|
|
+ WR32_sleep (HF_REG_BASE, HF_BASE_RESET);
|
|
|
+ WR32_sleep (HF_REG_BASE, 0);
|
|
|
+
|
|
|
/* reset DDR and FIFOs */
|
|
|
WR32_sleep (HF_REG_CONTROL,
|
|
|
HF_CONTROL_RESET |
|
|
|
HF_CONTROL_SOFT_RESET |
|
|
|
- 0x3 | /* what does this even mean? */
|
|
|
- HF_CONTROL_SOURCE_DCG);
|
|
|
+ HF_CONTROL_SOURCE_RX_FIFO);
|
|
|
|
|
|
/* write only in DDR mode, disable read */
|
|
|
- WR32_sleep (HF_REG_CONTROL, HF_CONTROL_SOURCE_DCG);
|
|
|
-
|
|
|
- /* reset DMA */
|
|
|
- WR32_sleep (HF_REG_BASE, HF_BASE_RESET);
|
|
|
- WR32_sleep (HF_REG_BASE, !HF_BASE_RESET);
|
|
|
+ WR32_sleep (HF_REG_CONTROL,
|
|
|
+ HF_CONTROL_SOURCE_RX_FIFO);
|
|
|
|
|
|
switch (opts->copy) {
|
|
|
case COPY_MEMCPY:
|
|
@@ -209,6 +209,10 @@ read_from_ddr (pcilib_t *pci, volatile void *bar, Options *opts)
|
|
|
HF_CONTROL_ENABLE_MULTI_READ |
|
|
|
HF_CONTROL_SOURCE_RX_FIFO);
|
|
|
|
|
|
+ WR32_sleep (HF_REG_CONTROL,
|
|
|
+ HF_CONTROL_ENABLE_READ |
|
|
|
+ HF_CONTROL_SOURCE_RX_FIFO);
|
|
|
+
|
|
|
/* DMA config */
|
|
|
WR32_sleep (HF_REG_NUM_PACKETS, 0x20);
|
|
|
WR32_sleep (HF_REG_PACKET_LENGTH, 0x20);
|
|
@@ -220,7 +224,7 @@ read_from_ddr (pcilib_t *pci, volatile void *bar, Options *opts)
|
|
|
|
|
|
/* start DMA */
|
|
|
if (!started) {
|
|
|
- WR32_sleep (0x04, 1);
|
|
|
+ WR32_sleep (HF_REG_DMA, HF_DMA_START);
|
|
|
started = 1;
|
|
|
}
|
|
|
|
|
@@ -232,13 +236,12 @@ read_from_ddr (pcilib_t *pci, volatile void *bar, Options *opts)
|
|
|
|
|
|
if (size > 0) {
|
|
|
WR64_sleep (HF_REG_DESCRIPTOR_ADDRESS, bus_addr);
|
|
|
- WR32_sleep (HF_REG_DMA, HF_DMA_START);
|
|
|
|
|
|
usleep (100);
|
|
|
fwrite (mem, 1, size, fp);
|
|
|
}
|
|
|
|
|
|
- WR32_sleep (HF_REG_DMA, HF_DMA_STOP);
|
|
|
+ /* WR32_sleep (HF_REG_DMA, HF_DMA_STOP); */
|
|
|
fclose (fp);
|
|
|
|
|
|
pcilib_free_kernel_memory (pci, kmem, KMEM_DEFAULT_FLAGS);
|