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Fix indentation

Matthias Vogelgesang 7 years ago
parent
commit
b2d177f868
1 changed files with 16 additions and 16 deletions
  1. 16 16
      hf-interface.h

+ 16 - 16
hf-interface.h

@@ -7,21 +7,21 @@
 #define HF_REG_DMA                      0x04
 #define HF_REG_PACKET_LENGTH            0x0C
 #define HF_REG_NUM_PACKETS              0x10
-#define HF_REG_INT_REG_VERSION		0x18
-#define HF_REG_PERF_COUNTER_4ns		0x1C
+#define HF_REG_INT_REG_VERSION          0x18
+#define HF_REG_PERF_COUNTER_4ns         0x1C
 #define HF_REG_PERF_COUNTER_FEEDBACK_1  0x20
 #define HF_REG_PERF_COUNTER_FEEDBACK_2  0x24
 #define HF_REG_PERF_COUNTER             0x28
-#define HF_REG_MULTI_2_EMPTY_COUNTER	0x30
+#define HF_REG_MULTI_2_EMPTY_COUNTER    0x30
 #define HF_REG_MULTI_2_FEEDBACK1        0x34
 #define HF_REG_MULTI_2_FEEDBACK2        0x38
 #define HF_REG_RESULT_LATENCY_MASTER    0x3C
-#define HF_REG_NUM_DESC_INSIDE		0x40
+#define HF_REG_NUM_DESC_INSIDE          0x40
 #define HF_REG_DESCRIPTOR_ADDRESS       0x50
 #define HF_REG_UPDATE_ADDRESS           0x58
 #define HF_REG_UPDATE_THRESHOLD         0x60
 #define HF_REG_TIMER_THRESHOLD          0x64
-#define HF_REG_DESCRIPTOR_AMD_SIGNAL	0x70
+#define HF_REG_DESCRIPTOR_AMD_SIGNAL    0x70
 
 #define HF_REG_CONF_DMA_TX_ENGINE       0x100
 #define HF_REG_LATENCY_NUM_MEAS         0x104
@@ -47,23 +47,23 @@
 #define HF_REG_DCG                      0x9000
 #define HF_REG_DCG_FIXED_PATTERN        0x9004
 #define HF_REG_DCG_FIXED_PATTERN_1ST    0x9008
-#define HF_REG_DCG_UPPER_LIMIT		0x900C
+#define HF_REG_DCG_UPPER_LIMIT          0x900C
 #define HF_REG_VERSION                  0x9030
 #define HF_REG_CONTROL                  0x9040
 #define HF_REG_INTERCONNECT             0x9048
-#define HF_REG_DDR_START_ADDR		0x9050
-#define HF_REG_DDR_UPPER_ADDR		0x9054
-#define HF_REG_DDR_RD_ADDR		0x9070
-#define HF_REG_DDR_WR_ADDR		0x9074
+#define HF_REG_DDR_START_ADDR           0x9050
+#define HF_REG_DDR_UPPER_ADDR           0x9054
+#define HF_REG_DDR_RD_ADDR              0x9070
+#define HF_REG_DDR_WR_ADDR              0x9074
 #define HF_REG_DFG_NUM_ROWS             0x9168
 #define HF_REG_DFG_NUM_FRAMES           0x9170
-#define HF_REG_DEBUG_RC_RESET		0x92e4
+#define HF_REG_DEBUG_RC_RESET           0x92e4
 #define HF_REG_DEBUG_REQUESTER_RESET    0x9344
 #define HF_REG_DEBUG_COMPLETER_RESET    0x93A4
 
 /* user register masks and values */
 
-#define HF_DCG_STOP			0x0
+#define HF_DCG_STOP                     0x00000000
 #define HF_DCG_START                    0x00000001
 #define HF_DCG_RESET                    0x00000010
 #define HF_DCG_ENABLE_FIXED_PATTERN     0x00000100
@@ -78,11 +78,11 @@
 #define HF_CONTROL_SOURCE_DFG           0x00020000
 #define HF_CONTROL_SOURCE_DCG_NO_DDR    0x00030000
 
-#define HF_INTERCONNECT_MASTER_DMA              0x2
-#define HF_INTERCONNECT_SLAVE_DMA               0x1
-#define HF_INTERCONNECT_DDR_TO_DMA              0x60
+#define HF_INTERCONNECT_SLAVE_DMA               0x001
+#define HF_INTERCONNECT_MASTER_DMA              0x002
+#define HF_INTERCONNECT_DDR_TO_DMA              0x060
 #define HF_INTERCONNECT_DDR_FROM_64             0x200
-#define HF_INTERCONNECT_DDR_FROM_CNT	        0x300
+#define HF_INTERCONNECT_DDR_FROM_CNT            0x300
 #define HF_INTERCONNECT_DDR_FROM_RX_MASTER      0x500
 
 #endif