#ifndef HF_INTERFACE_H
#define HF_INTERFACE_H

/* internal registers */

#define HF_REG_BASE                     0x00
#define HF_REG_DMA                      0x04
#define HF_REG_PACKET_LENGTH            0x0C
#define HF_REG_NUM_PACKETS              0x10
#define HF_REG_INT_REG_VERSION          0x18
#define HF_REG_PERF_COUNTER_4ns         0x1C
#define HF_REG_PERF_COUNTER_FEEDBACK_1  0x20
#define HF_REG_PERF_COUNTER_FEEDBACK_2  0x24
#define HF_REG_PERF_COUNTER             0x28
#define HF_REG_MULTI_2_EMPTY_COUNTER    0x30
#define HF_REG_MULTI_2_FEEDBACK1        0x34
#define HF_REG_MULTI_2_FEEDBACK2        0x38
#define HF_REG_RESULT_LATENCY_MASTER    0x3C
#define HF_REG_NUM_DESC_INSIDE          0x40
#define HF_REG_DESCRIPTOR_ADDRESS       0x50
#define HF_REG_UPDATE_ADDRESS           0x58
#define HF_REG_UPDATE_THRESHOLD         0x60
#define HF_REG_TIMER_THRESHOLD          0x64
#define HF_REG_DESCRIPTOR_AMD_SIGNAL    0x70

#define HF_REG_CONF_DMA_TX_ENGINE       0x100
#define HF_REG_LATENCY_NUM_MEAS         0x104
#define HF_REG_LATENCY_REPEAT_MASK      0x108
#define HF_REG_LATENCY_TIMEOUT          0x10C

#define HF_REG_DESC_LATENCY_DATA        0x110
#define HF_REG_DESC_LATENCY_RESULTS     0x118


/* internal register masks and values */

#define HF_BASE_RESET                   0x00000001
#define HF_BASE_VERSION                 0x0000FF00
#define HF_BASE_DATAPATH_WIDTH          0x000F0000
#define HF_BASE_FPGA_FAMILY             0xFF000000
#define HF_DMA_START                    0x1
#define HF_DMA_STOP                     0x0


/* user registers */

#define HF_REG_DCG                      0x9000
#define HF_REG_DCG_FIXED_PATTERN        0x9004
#define HF_REG_DCG_FIXED_PATTERN_1ST    0x9008
#define HF_REG_DCG_UPPER_LIMIT          0x900C
#define HF_REG_VERSION                  0x9030
#define HF_REG_CONTROL                  0x9040
#define HF_REG_INTERCONNECT             0x9048
#define HF_REG_DDR_START_ADDR           0x9050
#define HF_REG_DDR_UPPER_ADDR           0x9054
#define HF_REG_DDR_RD_ADDR              0x9070
#define HF_REG_DDR_WR_ADDR              0x9074
#define HF_REG_DFG_NUM_ROWS             0x9168
#define HF_REG_DFG_NUM_FRAMES           0x9170
#define HF_REG_DEBUG_RC_RESET           0x92e4
#define HF_REG_DEBUG_REQUESTER_RESET    0x9344
#define HF_REG_DEBUG_COMPLETER_RESET    0x93A4

/* user register masks and values */

#define HF_DCG_STOP                     0x00000000
#define HF_DCG_START                    0x00000001
#define HF_DCG_RESET                    0x00000010
#define HF_DCG_ENABLE_FIXED_PATTERN     0x00000100
#define HF_CONTROL_RESET                0x00000004
#define HF_CONTROL_SOFT_RESET           0x00000008
#define HF_CONTROL_ENABLE_READ          0x00000400
#define HF_CONTROL_ENABLE_MULTI_READ    0x00000800
#define HF_CONTROL_GLOBAL_COUNTER_RESET 0x00008000
#define HF_CONTROL_SOURCE_MASK          0x000F0000
#define HF_CONTROL_SOURCE_DCG           0x00000000
#define HF_CONTROL_SOURCE_RX_FIFO       0x00010000
#define HF_CONTROL_SOURCE_DFG           0x00020000
#define HF_CONTROL_SOURCE_DCG_NO_DDR    0x00030000

#define HF_INTERCONNECT_SLAVE_DMA               0x001
#define HF_INTERCONNECT_MASTER_DMA              0x002
#define HF_INTERCONNECT_DDR_TO_DMA              0x060
#define HF_INTERCONNECT_DDR_FROM_64             0x200
#define HF_INTERCONNECT_DDR_FROM_CNT            0x300
#define HF_INTERCONNECT_DDR_FROM_RX_MASTER      0x500

#endif