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+#!/bin/bash
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+######------------using new pll lmk03200-----#################
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+
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+# #####################---------SOLEIL---------------#################
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+# R0 (INIT) 0x80000100
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+# R0 0x00070E00
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+# R1 0x00000101
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+# R2 0x00000102
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+# R3 0x00070E03
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+# R4 0x00070E04
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+# R5 0x00070705
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+# R6 0x00070706
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+# R7 0x04000107
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+# R8 0x10000908
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+# R9 0xA0022A09
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+# R11 0x0082800B
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+# R13 0x028B000D
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+# R14 0x0830020E
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+# R15 0xC800380F
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+# ######################################################################
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+# echo "*PLL: calibration start ... "
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+# echo "*PLL: R0 Reset ... "
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+# pci -w 0x9064 0x80000000
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+# sleep 0.2
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+#
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+# echo "R0 (INIT)"
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+# pci -w 0x9064 0x90000100
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+# sleep 0.2
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+#
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+# echo "*PLL: R0 "
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+# pci -w 0x9064 0x00070E00 # OUTPUT 44 MHZ FPGA
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+# sleep 0.2
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+#
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+# echo "*PLL: R1 "
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+# pci -w 0x9064 0x00000101 # SYS_REF_2 before 0x00035C01
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+# sleep 0.2
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+#
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+# echo "*PLL: R2 "
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+# pci -w 0x9064 0x00000102 # SYS_REF_1
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+# sleep 0.2
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+#
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+# echo "*PLL: R3 "
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+# pci -w 0x9064 0x00070E03 #####remove later # clk_ADC_2 working:0x000704b3
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+# sleep 0.2
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+#
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+# echo "*PLL: R4 "
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+# pci -w 0x9064 0x00070E04 # d0,d4,d8,db # clk_ADC_1 working:0x000704b3
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+# sleep 0.2
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+#
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+# echo "*PLL: R5 "
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+# pci -w 0x9064 0x00070705 # FPGA_GTHX_CLOCK_0
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+# sleep 0.2
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+#
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+# echo "*PLL: R6 "
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+# pci -w 0x9064 0x00070706 # FPGA_GTHX_CLOCK_1
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+# sleep 0.2
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+#
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+# echo "*PLL: R7 "
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+# pci -w 0x9064 0x00000107 # FPGA_SYS_REF before 0x00035C07
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+# sleep 0.2
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+#
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+# echo "*PLL: R8 "
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+# pci -w 0x9064 0x10000908
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+# sleep 0.2
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+#
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+# echo "*PLL: R9 "
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+# pci -w 0x9064 0xA0022A09
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+# sleep 0.2
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+#
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+# echo "*PLL: RB (R11)"
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+# pci -w 0x9064 0x0082800B
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+# sleep 0.2
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+#
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+# echo "*PLL: RD (R13)"
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+# pci -w 0x9064 0x028B000D
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+# sleep 0.2
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+#
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+# echo "*PLL: RE (R14)"
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+# pci -w 0x9064 0x0830020E
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+# sleep 0.2
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+#
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+# echo "*PLL: RF (R15)"
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+# pci -w 0x9064 0xC8001C0F
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+# sleep 0.2
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+#
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+#
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+# ############################################
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+# echo "*PLL: STEP 2"
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+# ############################################
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+#
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+#
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+# echo "R0 (INIT)"
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+# pci -w 0x9064 0x08000100
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+# sleep 0.2
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+#
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+# echo "*PLL: R7 "
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+# pci -w 0x9064 0x04000107 # VCO divider bypassed
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+# sleep 0.2
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+#
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+# echo "*PLL: RF (R15)"
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+# pci -w 0x9064 0xC800380F
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+# sleep 0.2
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+#
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+# echo "R0 (INIT)"
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+# pci -w 0x9064 0x00070E00
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+# sleep 0.2
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+
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+
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+
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+#################-----KARA-----#######################################
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+# R0 (INIT) 0x80000100
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+# R0 0x00070A00
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+# R1 0x00000101
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+# R2 0x00000102
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+# R3 0x00070A03
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+# R4 0x00070A04
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+# R5 0x00070505
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+# R6 0x00070506
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+# R7 0x00000107
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+# R8 0x10000908
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+# R9 0xA0022A09
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+# R11 0x0082800B
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+# R13 0x028F800D
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+# R14 0x0830020E
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+# R15 0xC800280F
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+
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+###############-------------vco divider bypassed----#####
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+# R0 (INIT) 0x80000100
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+# R0 0x00070A00
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+# R1 0x00000101
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+# R2 0x00000102
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+# R3 0x00070A03
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+# R4 0x00070A04
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+# R5 0x00070505
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+# R6 0x00070506
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+# R7 0x04000107
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+# R8 0x10000908
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+# R9 0xA0022A09
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+# R11 0x0082800B
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+# R13 0x028F800D
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+# R14 0x0830020E
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+# R15 0xC800280F
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+
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+# ######################################################################
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+
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+
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+echo "*PLL: calibration start ... "
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+echo "*PLL: STEP 1"
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+
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+echo "*PLL: R0 Reset ... "
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+
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+
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+pci -w 0x9064 0x80000000
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+sleep 0.2
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+
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+echo "R0 (INIT)"
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+pci -w 0x9064 0x90000100
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+sleep 0.2
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+
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+echo "*PLL: R0 "
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+pci -w 0x9064 0x00070A00 # OUTPUT 44 MHZ FPGA
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+sleep 0.2
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+
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+echo "*PLL: R1 "
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+pci -w 0x9064 0x00000101 # SYS_REF_2 before 0x00035C01
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+sleep 0.2
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+#
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+echo "*PLL: R2 "
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+pci -w 0x9064 0x00000102 # SYS_REF_1
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+sleep 0.2
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+
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+echo "*PLL: R3 "
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+pci -w 0x9064 0x00070A03 #####remove later # clk_ADC_2 working:0x000704b3
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+sleep 0.2
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+
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+echo "*PLL: R4 "
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+pci -w 0x9064 0x00070A04 # d0,d4,d8,db # clk_ADC_1 working:0x000704b3
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+sleep 0.2
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+
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+echo "*PLL: R5 "
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+pci -w 0x9064 0x00070505 # FPGA_GTHX_CLOCK_0
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+sleep 0.2
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+
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+echo "*PLL: R6 "
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+pci -w 0x9064 0x00070506 # FPGA_GTHX_CLOCK_1
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+sleep 0.2
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+
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+echo "*PLL: R7 "
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+pci -w 0x9064 0x00000107 # FPGA_SYS_REF before 0x00035C07
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+sleep 0.2
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+
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+echo "*PLL: R8 "
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+pci -w 0x9064 0x10000908
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+sleep 0.2
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+
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+echo "*PLL: R9 "
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+pci -w 0x9064 0xA0022A09
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+sleep 0.2
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+
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+echo "*PLL: RB (R11)"
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+pci -w 0x9064 0x0082800B
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+sleep 0.2
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+
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+echo "*PLL: RD (R13)"
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+#pci -w 0x9064 0x028F800D
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+pci -w 0x9064 0x028300AD
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+sleep 0.2
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+
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+echo "*PLL: RE (R14)"
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+pci -w 0x9064 0x0830020E
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+sleep 0.2
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+
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+echo "*PLL: RF (R15)"
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+pci -w 0x9064 0xC800140F
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+sleep 0.2
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+
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+############################################
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+echo "*PLL: STEP 2"
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+############################################
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+
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+
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+echo "R0 (INIT)"
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+pci -w 0x9064 0x08000100
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+sleep 0.2
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+
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+echo "*PLL: R7 "
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+pci -w 0x9064 0x04000107 # VCO divider bypassed
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+sleep 0.2
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+
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+echo "*PLL: RF (R15)"
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+pci -w 0x9064 0xC800280F
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+sleep 0.2
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+
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+echo "R0 (INIT)"
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+pci -w 0x9064 0x00070A00
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+sleep 0.2
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