KALYPSO2_5_GUI/kalypso_registers.json

{

"INTEG_DURATION" : {
    "name" : "Integration Duration",
    "address" : "0x9000",
    "mask" : "0x000003FF",
    "notes": "GOTTHARD integration period (4ns step) 10 bits only"
  },

"INTEG_DELAY" : {
    "name" : "Integration Delay",
    "address" : "0x9004",
    "mask" : "0x000003FF",
    "notes": "GOTTHARD integration delay (4ns step) 10 bits only"
  },

"GOTT_GAIN" : {
    "name" : "Front-end electronics gain setting",
    "address" : "0x9010",
    "mask" : "0x0000000F",
    "notes": "Only 2 bits"
  },

"TIMESCAN" : {
    "name" : "Timescan function",
    "address" : "0x9014",
    "mask" : "0x00000001",
    "notes": "Timescan = EN"
  },

"GOTT_ODELAY_SET" : {
    "name" : "Output delay for front-end electronics",
    "address" : "0x9018",
    "mask" : "0x000000FF",
    "notes": "not used in this version"
  },

"FT_TO_ACQ" : {
    "name" : "Number of fast-triggers to acquire",
    "address": "0x9020",
    "mask" : "0xFFFFFFFF",
    "notes": ""
  },

"ST_TO_ACQ" : {
    "name" : "Number of slow-triggers to acquire",
    "address" : "0x9024",
    "mask" : "0xFFFFFFFF",
    "notes": ""
  },

"FT_SKIP" : {
    "name" : "Number of Fast triggers to skip",
    "address" : "0x9028",
    "mask" : "0xFFFFFFFF",
    "notes": ""
  },

"ST_SKIP" : {
    "name" : "Number of Slow Triggers to skip",
    "address" : "0x902C",
    "mask" : "0xFFFFFFFF",
    "notes": ""
  },

  "FRAME_RATE" : {
      "name" : "Time for total Acquisition",
      "address": "0x90C0",
      "mask" : "0xFFFFFFFF",
      "notes": "total orbits / (Value in hex * 220 ns) = Actual Frame rate "
    },

  "VERSION_REG" : {
    "name" : "Firmware version",
    "address" : "0x9030",
    "mask" : "0xFFFFFFFF",
    "notes": "Format 0xAAAA_BBBB where AAAA = KALYPSO version BBBB = firmware revision"
  },

  "ST_ACQ" : {
    "name" : "Number of Slow-triggers acquired",
    "address" : "0x9034",
    "mask" : "0xFFFFFFFF",
    "notes": ""
  },

  "FT_ACQ" : {
    "name" : "Number of Fast Triggers acquired",
    "address" : "0x9038",
    "mask" : "0xFFFFFFFF",
    "notes": ""
  },

  "CONTROL" : {
    "name" : "Control Register",
    "address" : "0x9040",
    "mask" : "0xFFFFFFFF",
    "notes": "Too many bits see User Manual!"
  },

  "CLK_DIV" : {
    "name" : "Clock divider for internal fast trigger generation",
    "address" : "0x9044",
    "mask" : "0xFFFFFFFF",
    "notes": "Divider of ADC CLK = 62.5 MHz. Set to 0 to enable external trigger."
  },

  "POWER" : {
    "name" : "Power configuration",
    "address" : "0x9048",
    "mask" : "0xFFFFFFFF",
    "notes": "Enables power supply chips on mezzanine card "
  },

  "KAL_CONF" : {
    "name" : "Advanced configuration",
    "address" : "0x904C",
    "mask" : "0xFFFFFFFF",
    "notes": "Advanced config. Used for testing and debugging..."
  },

  "STATUS_1" : {
    "name" : "Status register 1",
    "address" : "0x9050",
    "mask" : "0xFFFFFFFF",
    "notes": "See user manual for bit description"
  },

  "STATUS_2" : {
    "name" : "Status register 1",
    "address" : "0x9054",
    "mask" : "0xFFFFFFFF",
    "notes": "See user manual for bit description"
  },

  "STATUS_3" : {
    "name" : "Status register 1",
    "address" : "0x9058",
    "mask" : "0xFFFFFFFF",
    "notes": "See user manual for bit description"
  },

  "ADC_SPI" : {
    "name" : "SPI interface to ADC",
    "address" : "0x9060",
    "mask" : "0xFFFFFFFF",
    "notes": ""
  },

  "PLL_SPI" : {
    "name" : "SPI interface to PLL",
    "address" : "0x9064",
    "mask" : "0xFFFFFFFF",
    "notes": ""
  },

  "I2C_DAC_0" : {
    "name" : "I2C interface to DAC0",
    "address" : "0x9068",
    "mask" : "0xFFFFFFFF",
    "notes": ""
  },

  "I2C_DAC_1" : {
    "name" : "I2C interface to DAC1",
    "address" : "0x906C",
    "mask" : "0xFFFFFFFF",
    "notes": ""
  },

  "DDR_ADDR_WR" : {
    "name" : "BBB",
    "address" : "0x9074",
    "mask" : "0xFFFFFFFF",
    "notes": "Current WR Address in DDR"
  },

  "DDR_ADDR_RD_CUR" : {
    "name" : "I2C interface",
    "address" : "0x907C",
    "mask" : "0xFFFFFFFF",
    "notes": "Current RD Address in DDR"
  },

  "I2C_DAC_1" : {
    "name" : "BBB",
    "address" : "0x9078",
    "mask" : "0xFFFFFFFF",
    "notes": "Next WR Address in DDR"
  },

  "IDELAYS" : {
    "name" : "Configuration of IDELAY stage",
    "address" : "0x9080",
    "mask" : "0xFFFFFFFF",
    "notes": "Tuned by Lorenzo don't change!"
  },

  "ALIGN_ADC" : {
    "name" : "Pattern to align ADC",
    "address" : "0x9084",
    "mask" : "0xFFFFFFFF",
    "notes": "Align ADC pattern & Bits 13:0"
  },

  "CLOCK_PS" : {
    "name" : "Phase shift for output clock",
    "address" : "0x9088",
    "mask" : "0xFFFFFFFF",
    "notes": ""
  },

  "PCIE_RESET" : {
      "name" : "PCIe Id register",
      "address" : "0x0000",
      "mask" : "0xFFFFFFFF",
      "notes": "Register used to identify PCIe Board"
    }
}