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@@ -4,6 +4,7 @@ Configuration for each board
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import os
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import sys
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+import traceback
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if sys.version_info[:3] < (3,0):
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import ConfigParser as configparser
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else:
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@@ -466,6 +467,7 @@ class BoardConfiguration(QtGui.QWidget):
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callback(value)
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except Exception as e:
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log.error('Observer Callback error: {}'.format(e))
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+ print(traceback.format_exc())
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for cb in self._observers_for_all:
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try:
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@@ -482,6 +484,7 @@ class BoardConfiguration(QtGui.QWidget):
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callback(value)
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except Exception as e:
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log.error('Observer Callback error: {}'.format(e))
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+ print(traceback.format_exc())
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time.sleep(0.025)
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def _notify_observers(self, key, value, write=True):
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@@ -647,39 +650,112 @@ class BoardConfiguration(QtGui.QWidget):
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logging.error("Error in Board Communication, was unable to write value to board "+reason)
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def _set_adc_gain(self, x):
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- self._select_adc(1)
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+
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+ #Bits 1 and 2 of register 9044 control which SPI channels to select.
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+ #SPI_1 will route to ADC-Element 1 (Channel 1 and 2), and SPI_2
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+ #will route to ADC-Element 2 (Channel 3 and 4).
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+
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+ #Bits 16 and 17 of register 9044 control which FMCs to route the
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+ #SPI commands to. If both bits are 1, then the SPI commands get routed
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+ #to both FMCs at the same time.
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+
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+ #pci.read response is returned as a list. Since we expect only one
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+ #value, we access index [0]
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+ initial_mux_config = pci.read(self.identifier, reg='9044')[0]
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+
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+
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+ #Select SPI1 and FMC1
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+ updated_mux_config = initial_mux_config | 0x10002
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+ pci.write(self.identifier, hex(updated_mux_config), '0x9044')
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+
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pci.write(self.identifier, '46{:04x}'.format(int(x[0])), '0x9064')
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pci.write(self.identifier, '56{:04x}'.format(int(x[1])), '0x9064')
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- self._select_adc(3)
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+
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+ #Select SPI2 and FMC1
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+ updated_mux_config = initial_mux_config | 0x10004
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+ pci.write(self.identifier, hex(updated_mux_config), '0x9044')
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+
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pci.write(self.identifier, '46{:04x}'.format(int(x[2])), '0x9064')
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pci.write(self.identifier, '56{:04x}'.format(int(x[3])), '0x9064')
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- if len(x) > 4:
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- logging.vinfo("Gain update not defined for more than 4 adc")
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+
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+ if len(x) > 4 and len(x) < 9:
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+
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+ #Select SPI1 and FMC2
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+ updated_mux_config = initial_mux_config | 0x20002
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+ pci.write(self.identifier, hex(updated_mux_config), '0x9044')
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+
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+ pci.write(self.identifier, '46{:04x}'.format(int(x[4])), '0x9064')
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+ pci.write(self.identifier, '56{:04x}'.format(int(x[5])), '0x9064')
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+
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+
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+ #Select SPI2 and FMC2
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+ updated_mux_config = initial_mux_config | 0x20004
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+ pci.write(self.identifier, hex(updated_mux_config), '0x9044')
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+
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+ pci.write(self.identifier, '46{:04x}'.format(int(x[6])), '0x9064')
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+ pci.write(self.identifier, '56{:04x}'.format(int(x[7])), '0x9064')
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+
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+ else:
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+ logging.vinfo("Gain update not defined for more than 8 adc")
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+
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+
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+ #Restore the initial MUX Configuration
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+ pci.write(self.identifier, hex(initial_mux_config), '0x9044')
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+
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def _set_adc_offset(self, x):
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- #ADC1
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- self._select_adc(1)
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+
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+ #Bits 1 and 2 of register 9044 control which SPI channels to select.
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+ #SPI_1 will route to ADC-Element 1 (Channel 1 and 2), and SPI_2
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+ #will route to ADC-Element 2 (Channel 3 and 4).
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+
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+ #Bits 16 and 17 of register 9044 control which FMCs to route the
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+ #SPI commands to. If both bits are 1, then the SPI commands get routed
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+ #to both FMCs at the same time.
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+
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+ #pci.read response is returned as a list. Since we expect only one
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+ #value, we access index [0]
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+ initial_mux_config = pci.read(self.identifier, reg='9044')[0]
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+
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+
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+ #Select SPI1 and FMC1
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+ updated_mux_config = initial_mux_config | 0x10002
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+ pci.write(self.identifier, hex(updated_mux_config), '0x9044')
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+
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pci.write(self.identifier, '44{:04x}'.format(int(x[0])), '0x9064')
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pci.write(self.identifier, '54{:04x}'.format(int(x[1])), '0x9064')
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- self._select_adc(3)
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+
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+ #Select SPI2 and FMC1
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+ updated_mux_config = initial_mux_config | 0x10004
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+ pci.write(self.identifier, hex(updated_mux_config), '0x9044')
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+
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pci.write(self.identifier, '44{:04x}'.format(int(x[2])), '0x9064')
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pci.write(self.identifier, '54{:04x}'.format(int(x[3])), '0x9064')
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- if len(x) > 4:
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- logging.vinfo("Offset update not defined for more than 4 adc")
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-
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- def _select_adc(self, nr):
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- val = 0
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- if nr == 0:
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- val = 0
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- if nr < 3:
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- val = 4
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- elif nr < 5:
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- val = 2
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- pci.write(self.identifier, hex(val), '0x9044')
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+
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+ if len(x) > 4 and len(x) < 9:
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+
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+ #Select SPI1 and FMC2
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+ updated_mux_config = initial_mux_config | 0x20002
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+ pci.write(self.identifier, hex(updated_mux_config), '0x9044')
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+
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+ pci.write(self.identifier, '44{:04x}'.format(int(x[4])), '0x9064')
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+ pci.write(self.identifier, '54{:04x}'.format(int(x[5])), '0x9064')
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+
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+
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+ #Select SPI2 and FMC2
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+ updated_mux_config = initial_mux_config | 0x20004
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+ pci.write(self.identifier, hex(updated_mux_config), '0x9044')
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+
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+ pci.write(self.identifier, '44{:04x}'.format(int(x[6])), '0x9064')
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+ pci.write(self.identifier, '54{:04x}'.format(int(x[7])), '0x9064')
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+
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+ else:
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+ logging.vinfo("Offset update not defined for more than 8 adc")
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+
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def _set_samplingrate(self, rate):
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return
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