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@@ -4,11 +4,12 @@
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"sequence_names": [
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"reset_sequence",
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"PLL_sequence",
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+ "PLL_sequenceswitch",
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"PLL_sequence500",
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"PLL_sequence_1G",
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"synchronisation_sequence",
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- "adc_autosync",
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"calibartion_sequence",
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+ "adc_autosync",
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"adc_pdown",
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"adc_normal",
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"adc_test"],
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@@ -60,8 +61,8 @@
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]
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]
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},
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- "PLL_sequence500": {
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- "Comment": "PLL init SR:500MHz, ref:500MHz",
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+ "PLL_sequence": {
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+ "Comment": "PLL init SR:500MHz, ref:125MHz",
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"status_val" : "PLL500M",
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"sequence": [
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[
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@@ -87,10 +88,10 @@
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"delay_330_adc_2", "1"
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],
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[
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- "0x302000C2", "0x9060",
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+ "0x30140302", "0x9060",
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"",
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"CASCADE delay to +0*330ps",
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- "delay_cascade", "5"
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+ "delay_cascade", "0"
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],
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[
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"0x301800C3", "0x9060",
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@@ -99,9 +100,10 @@
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"delay_330_fpga", "1"
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],
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[
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- "0x80140184", "0x9060",
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+ "0x301800C4", "0x9060",
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"",
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- ""
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+ "FPGA OUTPUT new KaptureBoard",
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+ "delay_330_fpga", "1"
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],
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[
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"0x301400C5", "0x9060",
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@@ -117,10 +119,10 @@
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"delay_25_adc_2", "10"
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],
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[
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- "0x015001A7", "0x9060",
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+ "0x015001C7", "0x9060",
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"",
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- "CASCADE delay to +13*25ps",
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- "delay_cascade_25", "13"
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+ "CASCADE delay to +14*25ps",
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+ "delay_cascade_25", "14"
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],
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[
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"0x03010008", "0x9060",
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@@ -188,7 +190,7 @@
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""
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],
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[
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- "0x0080021C", "0x9060",
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+ "0x0020021C", "0x9060",
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"",
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""
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],
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@@ -198,7 +200,7 @@
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""
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],
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[
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- "0x0300005E", "0x9060",
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+ "0x0600009E", "0x9060",
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"",
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""
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],
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@@ -208,9 +210,28 @@
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""
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]
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]
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+ },
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+ "PLL_sequenceswitch": {
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+ "Comment": "PLL switch to ref:500MHz",
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+ "status_val" : "PLL500M",
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+ "sequence": [
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+
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+ [
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+ "0x302000C2", "0x9060",
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+ "",
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+ "CASCADE delay to +0*330ps",
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+ "delay_cascade", "5"
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+ ],
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+ [
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+ "0x301800C3", "0x9060",
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+ "",
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+ "FPGA OUTPUT",
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+ "delay_330_fpga", "1"
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+ ]
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+ ]
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},
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- "PLL_sequence": {
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- "Comment": "PLL init SR:500MHz, ref:125MHz",
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+ "PLL_sequence500": {
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+ "Comment": "PLL init SR:500MHz, ref:500MHz",
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"status_val" : "PLL500M",
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"sequence": [
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[
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@@ -236,10 +257,10 @@
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"delay_330_adc_2", "1"
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],
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[
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- "0x30140302", "0x9060",
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+ "0x302000C2", "0x9060",
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"",
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"CASCADE delay to +0*330ps",
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- "delay_cascade", "0"
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+ "delay_cascade", "5"
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],
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[
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"0x301800C3", "0x9060",
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@@ -248,10 +269,9 @@
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"delay_330_fpga", "1"
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],
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[
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- "0x301800C4", "0x9060",
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+ "0x80140184", "0x9060",
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"",
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- "FPGA OUTPUT new KaptureBoard",
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- "delay_330_fpga", "1"
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+ ""
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],
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[
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"0x301400C5", "0x9060",
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@@ -267,10 +287,10 @@
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"delay_25_adc_2", "10"
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],
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[
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- "0x015001C7", "0x9060",
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+ "0x015001A7", "0x9060",
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"",
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- "CASCADE delay to +14*25ps",
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- "delay_cascade_25", "14"
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+ "CASCADE delay to +13*25ps",
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+ "delay_cascade_25", "13"
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],
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[
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"0x03010008", "0x9060",
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@@ -338,7 +358,7 @@
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""
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],
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[
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- "0x0020021C", "0x9060",
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+ "0x0080021C", "0x9060",
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"",
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""
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],
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@@ -348,7 +368,7 @@
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""
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],
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[
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- "0x0600009E", "0x9060",
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+ "0x0300005E", "0x9060",
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"",
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""
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],
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@@ -358,7 +378,7 @@
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""
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]
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]
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- },
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+ },
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"PLL_sequence_1G": {
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"Comment": "PLL init SR:1GHz, ref:125MHz",
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"status_val" : "PLL1G",
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