11 Commits d7220d430b ... 3055d444ed

Author SHA1 Message Date
  kapture2 3055d444ed Added Frequency Divider Spinbox to interface 3 years ago
  Timo Dritschler 641d5f64fc Python2 compatibility fix 3 years ago
  Timo Dritschler d7714a1520 Added 7bit encoding controls 3 years ago
  Timo Dritschler 2abc3aa7aa Added ethernet socket to FrequencyExtractWidget 3 years ago
  Timo Dritschler d9bbb05ca8 Added new FrequencyExtractWidget 3 years ago
  Timo Dritschler 2135e66532 Fixed flipped register banks for Bunch Shifts 3 years ago
  kapture2 d7220d430b Added Frequency Divider Spinbox to interface 3 years ago
  Timo Dritschler ad8cc6a2ef Python2 compatibility fix 3 years ago
  Timo Dritschler e2105640ae Added 7bit encoding controls 3 years ago
  Timo Dritschler f0d6786764 Added ethernet socket to FrequencyExtractWidget 3 years ago
  Timo Dritschler b54294b9e8 Added new FrequencyExtractWidget 3 years ago
1 changed files with 14 additions and 3 deletions
  1. 14 3
      KCG/base/backend/board/board_config.py

+ 14 - 3
KCG/base/backend/board/board_config.py

@@ -589,9 +589,17 @@ class BoardConfiguration(QtGui.QWidget):
     def _set_bunch_shift(self, values):
         #print("Setting bunch shifts: ", values)
 
+        #Banks are flipped!
+        #0x9320:  5,6,7,8
+        #0x9330:  1,2,3,4
+
+        bank1 = values[4:8]
+        bank2 = values[0:4]
+        adcs = bank1 + bank2
+
         base_reg = 0x9320
 
-        for i, val in enumerate(values):
+        for i, val in enumerate(adcs):
             reg = hex(base_reg+(i*4))
             set = "0x{0:08x}".format(val)
 
@@ -732,10 +740,13 @@ class BoardConfiguration(QtGui.QWidget):
             self.update('chip_delay', tmp , write=False)    
 
             # --[ read bunch shifts ] --
-            bunch_shifts = pci.read(self.identifier, reg='9320', amount=4, decimal=True)
+            #Banks are flipped!
+            #0x9320:  5,6,7,8
+            #0x9330:  1,2,3,4
+            bunch_shifts = pci.read(self.identifier, reg='9330', amount=4, decimal=True)
 
             if adc_number > 4:
-                bunch_shifts = bunch_shifts + pci.read(self.identifier, reg='9330', amount=4, decimal=True)
+                bunch_shifts = bunch_shifts + pci.read(self.identifier, reg='9320', amount=4, decimal=True)
             self.update('bunch_shift', bunch_shifts, write=False)    
 
             # --[ read and set th delay ]--