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- """
- Sequences for various board actions
- These methods are generators that will yield as first element the number
- of actions (other yields) excluding it self
- They will then perform the next action in row (setting registers or reading values from boards etc)
- and will yield True or False depending on the result of the action performed
- """
- import logging
- from . import *
- from utils import *
- def startup_sequence(board_id):
- NUMBER = 4
- yield NUMBER
- pci.start_dma(board_id)
- pci.write(board_id, '0x20001000', '0x9100')
- pci.write(board_id, '0x05', '0x9040')
- yield True
- pci.write(board_id, '0x3C1', '0x9040')
- logging.info("9040: " + str(pci.read(board_id, 1, '0x9040')[0]))
- yield True
- pci.write(board_id, '0x3F1', '0x9040')
- logging.info("9040: " + str(pci.read(board_id, 1, '0x9040')[0]))
- yield True
- pci.write(board_id, '0x3F0', '0x9040')
- logging.info("9040: " + str(pci.read(board_id, 1, '0x9040')[0]))
- yield True
- def calibration_sequence(board_id):
- NUMBER = 15
- yield NUMBER
- # Removing Board Reset
- pci.write(board_id, '0x2000003f0', '0x9040')
- yield True
- # SPI Fanout Programming...
- pci.write(board_id, '0x083', '0x9068')
- yield True
- pci.write(board_id, '0x6a2', '0x9068')
- yield True
- # PLL calibration start...
- # PLL Reset...
- pci.write(board_id, '0x80000000', '0x9060')
- yield True
- # Set CH_0 (FPGA) clock FPGA ...
- pci.write(board_id, '0x00050000', '0x9060')
- yield True
- # Set CH_3 clock fanout ...
- pci.write(board_id, '0x00050003', '0x9060')
- yield True
- # Set CH_4 clock ADC 1 ...
- pci.write(board_id, '0x00050004', '0x9060')
- yield True
- # Set CH_5 clock ADC 2 ...
- pci.write(board_id, '0x00050005', '0x9060')
- yield True
- # Set CH_6 clock ADC 3 ...
- pci.write(board_id, '0x00050006', '0x9060')
- yield True
- # Set CH_7 clock ADC 4 ...
- pci.write(board_id, '0x00050007', '0x9060')
- yield True
- # Set R8 ...
- pci.write(board_id, '0x10000908', '0x9060')
- yield True
- # Set R11 ...
- pci.write(board_id, '0x0082800B', '0x9060')
- yield True
- # Set R13 ...
- pci.write(board_id, '0x029F400D', '0x9060')
- yield True
- # Set R14 (F_out and Global_EN => ON) ...
- pci.write(board_id, '0x0830040E', '0x9060')
- yield True
- # Set R15 ...
- pci.write(board_id, '0xD000100F', '0x9060')
- yield True
- def synchronisation_sequence(board_id):
- NUMBER = 2
- yield NUMBER
- # Send the PLL sync signals ...
- pci.write(board_id, '0x1003f0', '0x9040')
- yield True
- pci.write(board_id, '0x0003f0', '0x9040')
- yield True
- def write_value_sequence(board_id):
- NUMBER = 8
- yield NUMBER
- # Set_FPGA_clock_delay.sh 0
- get_board_config(board_id).set_fpga_delay(get_board_config(board_id).get('fpga_delay'))
- yield True
- # Set_Delay_chip.sh 16 16 16 16
- factors = [get_board_config(board_id).get('chip_1_delay'), get_board_config(board_id).get('chip_2_delay'),
- get_board_config(board_id).get('chip_3_delay'), get_board_config(board_id).get('chip_4_delay')]
- get_board_config(board_id).set_chip_delay([0, 1, 2, 3], factors)
- yield True
- # Set_TH_Delay.sh 12
- get_board_config(board_id).set_th_delay(get_board_config(board_id).get('th_delay'))
- yield True
- # Set_ADC_1_Delay.sh 4
- get_board_config(board_id).set_adc_delay(0, get_board_config(board_id).get('adc_1_delay'))
- yield True
- # Set_ADC_2_Delay.sh 4
- get_board_config(board_id).set_adc_delay(1, get_board_config(board_id).get('adc_2_delay'))
- yield True
- # Set_ADC_3_Delay.sh 4
- get_board_config(board_id).set_adc_delay(2, get_board_config(board_id).get('adc_3_delay'))
- yield True
- # Set_ADC_4_Delay.sh 4
- get_board_config(board_id).set_adc_delay(3, get_board_config(board_id).get('adc_4_delay'))
- yield True
- pci.write(board_id, '{0:08x}'.format(get_board_config(board_id).get('orbits_observe')), '0x9020')
- yield True
- pci.write(board_id, '{0:08x}'.format(get_board_config(board_id).get('orbits_skip')), '0x9028')
- yield True
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