Master_BMS/BMS Master/Project_Settings/Startup_Code/MPC5646C_HWInit.c

/*
 *
 * FILE : MPC564xBC_HWInit.c
 *
 * DESCRIPTION:
 *  This file contains all MPC564xBC derivative needed initializations, 
 *  and all initializations for the MPC564xBC boards which are supported.
 *  This includes setting up the External Bus Interface to allow access
 *  to memory on the external bus, and ensuring there is a valid entry in
 *  the MMU for the external memory access.
 */

/*----------------------------------------------------------------------------*/
/* Includes                                                                   */
/*----------------------------------------------------------------------------*/

#include "MPC5646C.h"       /* MPC55xx platform development header            */
#include "MPC5646C_HWInit.h"

#ifdef __cplusplus
extern "C" {
#endif

/*******************************************************/
/* MPC564xBC derivative specific hardware initialization */
/*******************************************************/

/*----------------------------------------------------------------------------*/
/* Function declarations                                                      */
/*----------------------------------------------------------------------------*/

/* All these functions must be located in the initial 4KB memory window (.init) 
	and implemented "nofralloc" so as to not use the stack */

/* Memory initialization */
__declspec(section ".init") __asm void INIT_Derivative(void);

/* Write one MMU Table Entry */
__declspec(section ".init") __asm void WriteMMUTableEntry( void );

/* Initialize the needed MMU Table entries */
__declspec(section ".init") __asm void __initMMU(void);

/* Configures the SWT */
__declspec(section ".init") __asm void cfg_WATCHDOG(void);

/* Configures the platform flash register. */
__declspec(section ".init") __asm void __FlashConfig(void);

/* This macro allows to use C defined address with the inline assembler */
#define MAKE_HLI_COMPATIBLE(hli_name, c_expr) enum { hli_name=/*lint -e30*/((int)(c_expr)) };


/*----------------------------------------------------------------------------*/
/* Function implementations                                                   */
/*----------------------------------------------------------------------------*/

/* Symbol L2SRAM_LOCATION is defined in the application linker command file (.lcf) 
   It is defined to the start of the L2SRAM of the MPC564xBC. 
*/
/*lint -esym(752, L2SRAM_LOCATION) */
extern long L2SRAM_LOCATION;  

/* Symbol L2SRAM_CNT is defined in the application linker command file (.lcf)
   It represents the how many writes with stmw,128 bytes each, are needed to cover
   the whole L2SRAM.
*/
extern long L2SRAM_CNT;

/**************************************************************************/
/* FUNCTION     : cfg_WATCHDOG                                            */
/* PURPOSE      : This function configures the WATCHDOG					  */
/*                SEQUENCE:                                               */
/*                - Disable watchdog, 								      */
/**************************************************************************/
MAKE_HLI_COMPATIBLE(SR_WSC_1, 50464)
MAKE_HLI_COMPATIBLE(SR_WSC_2, 55592)
MAKE_HLI_COMPATIBLE(CR_VALUE, 0x8000010A)

/** Address of the SWT SR */
MAKE_HLI_COMPATIBLE(SWT_SR, &SWT.SR.R)
/** Address of the SWT CR */
MAKE_HLI_COMPATIBLE(SWT_CR, &SWT.CR.R)

__asm void cfg_WATCHDOG(void)
{
	nofralloc

	/* Clear the soft lock bit SWT_CR.SLKSWT_CR: */
	/* SR --> 0x0000c520 */
    lis r4, 0
    ori r4, r4, SR_WSC_1@l
    lis r3, SWT_SR@ha
    stw r4, SWT_SR@l(r3)
    /* SR --> 0x0000d928 */
    lis r4, 0
    ori r4, r4, SR_WSC_2@l
    stw r4, SWT_SR@l(r3)

    /* Disable watchdog, SWT.CR.WEN = 0*/
    lis r4, CR_VALUE@h
    ori r4, r4, CR_VALUE@l
    lis r3, SWT_CR@ha
    stw r4, SWT_CR@l(r3)

	blr
}

/** PFCR0 */
MAKE_HLI_COMPATIBLE(PFCR0, &CFLASH_0.PFCR0.R)
//bit 0 -> bit 31
//B02_APC  = 0b00000, Accesses may be initiated on consecutive (back-to-back) cycles
//B02_WWSC = 0b00001, Write: 1 additional wait-state is added
//B02_RWSC = 0b00101, >100 MHz - 120 MHz, APC =RWSC=5 (default reset)
//B02_RWWC[2:1] = 0b11, Generate a bus stall for a read while write/erase, disable the stall notification interrupt,disable the abort + abort notification interrupt (reset default)
//B02_P1_BCFG = 0b11,The buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and buffer 3 for data accesses.(reset default)
//B02_P1_DPFE = 0b0 (reset default)
//B02_P1_IPFE = 0b1 (reset default)
//B02_P1_PFLM = 0b10 (reset default)
//B02_P1_BFE  = 0b1 (reset default)
//B02_RWWC0   = 0b1 (reset default)
//B02_P0_BCFG = 0b11 (reset default)
//B02_P0_DPFE = 0b0 (reset default)
//B02_P0_IPFE = 0b1 (reset default)
//B02_P0_PFLM = 0b10 (reset default)
//B02_P0_BFE  = 0b1 (reset default)
MAKE_HLI_COMPATIBLE(FLASH_DATA0, 0x4BEDED) 
// reset value 0x294BEDED

/** PFCR1 */
MAKE_HLI_COMPATIBLE(PFCR1, &CFLASH_0.PFCR1.R)
//bit 0 -> bit 31
//B1_APC    = 0b00000 Accesses may be initiated on consecutive (back-to-back) cycles
//B1_WWSC   = 0b00001 write: 1 additional wait-state is added
//B1_RWSC   = 0b00101 >100 MHz - 120 MHz, APC =RWSC=5
//B1_RWWC2:1= 0b11 Generate a bus stall for a read while write/erase, disable the stall notification interrupt,disable the abort + abort notification interrupt (reset default)
//0b000000
//B1_P1_BFE = 0b1 Bank1, Port 1 Buffer Enable (reset default)
//B1_RWWC0  = 0b1 Generate a bus stall for a read while write/erase, disable the stall notification interrupt,disable the abort + abort notification interrupt (reset default)
//0b000000
//B1_P0_BFE = 0b1 Bank1, Port 0 Buffer Enable (reset default)
MAKE_HLI_COMPATIBLE(FLASH_DATA1, 0x4B8181)
// reset value 0x6b5b8181

MAKE_HLI_COMPATIBLE(__FlashConfigInstrCount, 16)
__asm void __FlashConfig(void) 
{
	nofralloc
	/* configure code flash PFCR0 */
	lis r4, PFCR0@h
	ori r4, r4, PFCR0@l
	lis r3, FLASH_DATA0@h
	ori r3, r3, FLASH_DATA0@l
	stw r3, 0(r4) /* stw r3,(0)r4 machine code: writes r3 contents to addr in r4 */
	mbar 0 /* msync machine code: ensure prior store completed */

	/* configure code flash PFCR1 */
	lis r4, PFCR1@h
	ori r4, r4, PFCR1@l
	lis r3, FLASH_DATA1@h
	ori r3, r3, FLASH_DATA1@l
	stw r3, 0(r4) /* stw r3,(0)r4 machine code: writes r3 contents to addr in r4 */
	mbar 0 /* mbar machine code: ensure prior store completed */
	blr
	nop
	nop
	nop
}

/**
 * TLB_Entry_15: default page for running the initialization code, TS=1, 4GB, cache inhibited,
 * not guarded, big endian.
 */
MAKE_HLI_COMPATIBLE(TLB_Entry_15_MAS0, MAS0_VALUE(15))
MAKE_HLI_COMPATIBLE(TLB_Entry_15_MAS1, MAS1_VALUE(V_VALID, IPROT_NOTPROTECTED, TID_GLOBAL, TS_ON, TSIZE_4GB))
MAKE_HLI_COMPATIBLE(TLB_Entry_15_MAS1_INVALID, MAS1_VALUE(V_INVALID, IPROT_NOTPROTECTED, TID_GLOBAL, TS_ON, TSIZE_4GB))
#if __option(vle)
MAKE_HLI_COMPATIBLE(TLB_Entry_15_MAS2, MAS2_VALUE(0, VLE_MODE, WRITE_BACK, CACHE_INHIBIT, MEM_COHERENCE_NREQ, NOT_GUARDED, BIG_ENDIAN))
#else
MAKE_HLI_COMPATIBLE(TLB_Entry_15_MAS2, MAS2_VALUE(0, BOOK_E_MODE, WRITE_BACK, CACHE_INHIBIT, MEM_COHERENCE_NREQ, NOT_GUARDED, BIG_ENDIAN))
#endif
MAKE_HLI_COMPATIBLE(TLB_Entry_15_MAS3, MAS3_VALUE(0, READ_WRITE_EXECUTE))

__asm void INIT_Derivative(void) 
{
nofralloc

	/* Create initialization memory space required in order to create
	TLB entries for FLASH or RAM. */
	lis r3, TLB_Entry_15_MAS0@h
	ori r3, r3, TLB_Entry_15_MAS0@l
	lis r4, TLB_Entry_15_MAS1@h
	ori r4, r4, TLB_Entry_15_MAS1@l
	xor r5, r5, r5
	mr r6, r5
	ori r5, r5, TLB_Entry_15_MAS2@l
	ori r6, r6, TLB_Entry_15_MAS3@l

    mtspr 624, r3
    mtspr 625, r4
    mtspr 626, r5
    mtspr 627, r6
    
    /* prefetch instruction to this point. */
    isync
    tlbwe
    /* make sure isntructions and data are fetched from the new context. */
    msync
    isync

    /* force this TLB entry to be used for translation */
    mfmsr r10
    /* save state */
    mr r3, r10
    /* set IS=1, DS=1 */
    ori r3, r3, 0x20
    isync
    /* mtmsr does execution synchronization.*/
    mtmsr r3
    /* Required after changing MSR.IS, and MSR.DS so the prefetched instructions
     will be discarded and all subsequent instructions will use the TLB 15 context.
     */
    isync

    /* create device specific MMU entries */
   	mflr	r26
   	bl __initMMU
   	mtlr	r26
   	
	/* Disable the software watch dog. */
	mflr	r26
	bl cfg_WATCHDOG
	mtlr	r26

	/* MPC564xBC L2SRAM initialization code */
#if defined(ROM_VERSION)
    /* SRAM initialization code*/
    lis r11,L2SRAM_LOCATION@h
    ori r11,r11,L2SRAM_LOCATION@l

    /* Loops to cover L2SRAM, stmw allows 128 bytes (32 GPRS x 4 bytes) writes */
    lis r12,L2SRAM_CNT@h
    ori r12,r12,L2SRAM_CNT@l
    mtctr r12

    init_l2sram_loop:
        stmw r0, 0(r11)        /* Write 32 GPRs to SRAM*/
        addi r11,r11,128      /* Inc the ram ptr; 32 GPRs * 4 bytes = 128B */
        bdnz init_l2sram_loop /* Loop for 48k of SRAM */

   	// init platform flash registers from RAM - please see reference manual
    lis r3,__FlashConfig@h
  	ori r3,r3,__FlashConfig@l

  	lis r4, __FlashConfigInstrCount@h
    ori r4, r4, __FlashConfigInstrCount@l
    mtctr r4
    lis r5, L2SRAM_LOCATION@h

    mflr r26 /* save LR */
    mtlr r5 /* set LR <- __FlashConfig*/

    /* copy function code to RAM */
    copy:
    lwz r6, 0(r3)
    stw r6, 0(r5)
    addi r3, r3, 4
    addi r5, r5, 4
    bdnz copy /* decrement CTR */
    blrl /* goto copyied __FlashConfig in RAM */
    mtlr r26 /* restore LR */
#endif
    
    /* restore msr */
    mtmsr r10
    /* execute all instructions and discard the prefetched instructions */
    isync

    /* invalidated initialization TLB entry 15 */
	lis r3, TLB_Entry_15_MAS0@h
	ori r3, r3, TLB_Entry_15_MAS0@l
	lis r4, TLB_Entry_15_MAS1_INVALID@h
	ori r4, r4, TLB_Entry_15_MAS1_INVALID@l
	mtspr 624, r3
    mtspr 625, r4
    tlbwe
    
    /* make sure isntructions and data are fetched from the new context. */
    isync
    msync

    blr
}

/* Initialize the needed MMU Table entries */

/* FLASH: TLB entry 0, Base address = 0x0000_0000, 16 MB, protected, guarded, cache on, big-endian, all access */
MAKE_HLI_COMPATIBLE(TLB_Entry_0_MAS0, MAS0_VALUE(0))
MAKE_HLI_COMPATIBLE(TLB_Entry_0_MAS1, MAS1_VALUE(V_VALID, IPROT_PROTECTED, TID_GLOBAL, TS_OFF, TSIZE_16MB))
#if __option(vle)
MAKE_HLI_COMPATIBLE(TLB_Entry_0_MAS2, MAS2_VALUE(0, VLE_MODE, WRITE_BACK, CACHEABLE, MEM_COHERENCE_NREQ, GUARDED, BIG_ENDIAN))
#else
MAKE_HLI_COMPATIBLE(TLB_Entry_0_MAS2, MAS2_VALUE(0, BOOK_E_MODE, WRITE_BACK, CACHEABLE, MEM_COHERENCE_NREQ, GUARDED, BIG_ENDIAN))
#endif
MAKE_HLI_COMPATIBLE(TLB_Entry_0_MAS3, MAS3_VALUE(0, READ_WRITE_EXECUTE))

/* SRAM: TLB entry 1, Base address = 0x4000_0000, 256K, not protected, not guarded, cache off, big-endian, all access */
MAKE_HLI_COMPATIBLE(TLB_Entry_1_MAS0, MAS0_VALUE(1))
MAKE_HLI_COMPATIBLE(TLB_Entry_1_MAS1, MAS1_VALUE(V_VALID, IPROT_NOTPROTECTED, TID_GLOBAL, TS_OFF, TSIZE_256KB))
#if __option(vle)
MAKE_HLI_COMPATIBLE(TLB_Entry_1_MAS2, MAS2_VALUE(0x40000, VLE_MODE, WRITE_BACK, CACHE_INHIBIT, MEM_COHERENCE_NREQ, NOT_GUARDED, BIG_ENDIAN))
#else
MAKE_HLI_COMPATIBLE(TLB_Entry_1_MAS2, MAS2_VALUE(0x40000, BOOK_E_MODE, WRITE_BACK, CACHE_INHIBIT, MEM_COHERENCE_NREQ, NOT_GUARDED, BIG_ENDIAN))
#endif
MAKE_HLI_COMPATIBLE(TLB_Entry_1_MAS3, MAS3_VALUE(0x40000, READ_WRITE_EXECUTE))

/* Peripheral bridge 1: TLB entry 2 Base address = 0xC000_0000, 64M, not protected, not guarded, cache off, big-endian, all access */
MAKE_HLI_COMPATIBLE(TLB_Entry_2_MAS0, MAS0_VALUE(2))
MAKE_HLI_COMPATIBLE(TLB_Entry_2_MAS1, MAS1_VALUE(V_VALID, IPROT_NOTPROTECTED, TID_GLOBAL, TS_OFF, TSIZE_64MB))
#if __option(vle)
MAKE_HLI_COMPATIBLE(TLB_Entry_2_MAS2, MAS2_VALUE(0xC0000, VLE_MODE, WRITE_BACK, CACHE_INHIBIT, MEM_COHERENCE_NREQ, NOT_GUARDED, BIG_ENDIAN))
#else
MAKE_HLI_COMPATIBLE(TLB_Entry_2_MAS2, MAS2_VALUE(0xC0000, BOOK_E_MODE, WRITE_BACK, CACHE_INHIBIT, MEM_COHERENCE_NREQ, NOT_GUARDED, BIG_ENDIAN))
#endif
MAKE_HLI_COMPATIBLE(TLB_Entry_2_MAS3, MAS3_VALUE(0xC0000, READ_WRITE_EXECUTE))

/* Peripheral bridge 0 + BAM: TLB entry 3 Base address = 0xFFE0_0000, 2M, not protected, not guarded, cache off, big-endian, all access */
MAKE_HLI_COMPATIBLE(TLB_Entry_3_MAS0, MAS0_VALUE(3))
MAKE_HLI_COMPATIBLE(TLB_Entry_3_MAS1, MAS1_VALUE(V_VALID, IPROT_NOTPROTECTED, TID_GLOBAL, TS_OFF, TSIZE_2MB))
#if __option(vle)
MAKE_HLI_COMPATIBLE(TLB_Entry_3_MAS2, MAS2_VALUE(0xFFE00, VLE_MODE, WRITE_BACK, CACHE_INHIBIT, MEM_COHERENCE_NREQ, NOT_GUARDED, BIG_ENDIAN))
#else
MAKE_HLI_COMPATIBLE(TLB_Entry_3_MAS2, MAS2_VALUE(0xFFE00, BOOK_E_MODE, WRITE_BACK, CACHE_INHIBIT, MEM_COHERENCE_NREQ, NOT_GUARDED, BIG_ENDIAN))
#endif
MAKE_HLI_COMPATIBLE(TLB_Entry_3_MAS3, MAS3_VALUE(0xFFE00, READ_WRITE_EXECUTE))

__asm void __initMMU(void)
{
nofralloc

     mflr     r27

     /* Configure FLASH page on TLB entry 0 */
     lis r3, TLB_Entry_0_MAS0@h
     ori r3, r3, TLB_Entry_0_MAS0@l
     lis r4, TLB_Entry_0_MAS1@h
     ori r4, r4, TLB_Entry_0_MAS1@l
     lis r5, TLB_Entry_0_MAS2@h
     ori r5, r5, TLB_Entry_0_MAS2@l
     lis r6, TLB_Entry_0_MAS3@h
     ori r6, r6, TLB_Entry_0_MAS3@l
     bl WriteMMUTableEntry

     /* Configure RAM page on TLB entry 1 */
     lis r3, TLB_Entry_1_MAS0@h
     ori r3, r3, TLB_Entry_1_MAS0@l
     lis r4, TLB_Entry_1_MAS1@h
     ori r4, r4, TLB_Entry_1_MAS1@l
     lis r5, TLB_Entry_1_MAS2@h
     ori r5, r5, TLB_Entry_1_MAS2@l
     lis r6, TLB_Entry_1_MAS3@h
     ori r6, r6, TLB_Entry_1_MAS3@l
     bl WriteMMUTableEntry 

     /* Peripheral bridge 0 on TLB entry 2 */
     lis r3, TLB_Entry_2_MAS0@h
     ori r3, r3, TLB_Entry_2_MAS0@l
     lis r4, TLB_Entry_2_MAS1@h
     ori r4, r4, TLB_Entry_2_MAS1@l
     lis r5, TLB_Entry_2_MAS2@h
     ori r5, r5, TLB_Entry_2_MAS2@l
     lis r6, TLB_Entry_2_MAS3@h
     ori r6, r6, TLB_Entry_2_MAS3@l
     bl WriteMMUTableEntry

     /* Peripheral bridge 0 on TLB entry 3 */
     lis r3, TLB_Entry_3_MAS0@h
     ori r3, r3, TLB_Entry_3_MAS0@l
     lis r4, TLB_Entry_3_MAS1@h
     ori r4, r4, TLB_Entry_3_MAS1@l
     lis r5, TLB_Entry_3_MAS2@h
     ori r5, r5, TLB_Entry_3_MAS2@l
     lis r6, TLB_Entry_3_MAS3@h
     ori r6, r6, TLB_Entry_3_MAS3@l
     bl WriteMMUTableEntry

     mtlr r27

     blr
}

/* Write one MMU Table Entry:               */
/* r3, r4, r5 and r6 must hold              */
/* the values of MAS0, MAS1, MAS2 and MAS3  */
__asm void WriteMMUTableEntry( void )
{ 
nofralloc

    /* Write MMU Assist Register 0 (MAS0); SPR 624 */
    mtspr   624, r3
    /* Write MMU Assist Register 1 (MAS1); SPR 625 */
    mtspr   625, r4
    /* Write MMU Assist Register 2 (MAS2); SPR 626 */
    mtspr   626, r5
    /* Write MMU Assist Register 3 (MAS3); SPR 627 */
    mtspr   627, r6
    /* Write the table entry */

    /* All instruction will complete here in current context. */
    //isync

    tlbwe

    /* synchronize instruction fetches and data accesses in respect
     with the new created TLB entry. */
    msync
    isync

    blr
}

#ifdef __cplusplus
}
#endif