Master_BMS/BMS Master/Sources/DSPI.c

//==============================================================================
// Purpose:    SPI Interface für das DSPI-Modul des MPC5646
//
// Created on:  20.04.2012 by IPE
//
// History
//		20.04.2012 neu, T.Maurer
//==============================================================================


#include "BMS_Master.h"



/*
const DSPI_config_t SPI_1_Config = {
	&DSPI_1,
	DSPI_Slave,
	16,	//FrameSize
	DSPI_ClassicFormat,
	DSPI_Baud15MHz,
	0,
	0,
	0,
	1,
	DSPI1_PortE4
};
*/



const DSPI_config_t SPI_6_Config = {
	&DSPI_6,
	DSPI_Master,
	16,	//FrameSize
	DSPI_ClassicFormat,
	DSPI_Baud2MHz,
	4,
	4,
	10,
	1,
	CS_Cont_ON,	//enum{CS_Cont_ON, CS_Cont_OFF};
	DSPI6_PortG14
};



// ----------------------------------------------------------------------------

int8_t DSPI_init(DSPI_config_t *const Config) 
{
	volatile struct DSPI_tag *p_DSPI;
	p_DSPI = Config->p_Modul;

  // -------------------------------------------------------------------
  // DSPI_0.MCR.R = 0x80010001;     // Configure DSPI_0 as master, and HALT the DSPI module für reg configuration //

	p_DSPI->MCR.B.MSTR 			= (Config->MaSlv_Mode==DSPI_Master) ? 1:0;		// 1: Master Mode, 0:Slave Mode
	p_DSPI->MCR.B.CONT_SCKE		= 0;		// 0: Continuous serial clock: disabled
	p_DSPI->MCR.B.DCONF			= 0b00;		// 00: SPI Mode, 01 DSI Mode, 10:CSI Mode
	p_DSPI->MCR.B.FRZ			= 0b0;		// FREEZE: 0; if Freeze=1, tx will be stopped on next frame tx in DEBUG
	p_DSPI->MCR.B.MTFE 			= (Config->TimingFormat==DSPI_ModifiedFormat) ? 1:0;		// Modified Timing Format Enable; 0: disabled
	p_DSPI->MCR.B.PCSSE			= 0b0;		// Peripheral chip select strobe enable; 0:0  CS5_x is used as the Peripheral chip select 5 signal
	p_DSPI->MCR.B.ROOE			= 0b0;		// Recieve FIFO Overflow Overwrite; 0: incoming data is ignored, 1: Incoming data is shifted in register

	p_DSPI->MCR.B.PCSIS5		= (Config->Std_CS_Mask & 32) ? 1:0;		// Peripheral Chip Select 5 inactive state: 0: inactiv CS=low
	p_DSPI->MCR.B.PCSIS4		= (Config->Std_CS_Mask & 16) ? 1:0;		// Peripheral Chip Select 4 inactive state: 0: inactiv CS=low
 	p_DSPI->MCR.B.PCSIS3		= (Config->Std_CS_Mask & 8) ? 1:0;		// Peripheral Chip Select 3 inactive state: 0: inactiv CS=low
	p_DSPI->MCR.B.PCSIS2		= (Config->Std_CS_Mask & 4) ? 1:0;		// Peripheral Chip Select 2 inactive state: 0: inactiv CS=low
	p_DSPI->MCR.B.PCSIS1		= (Config->Std_CS_Mask & 2) ? 1:0;		// Peripheral Chip Select 1 inactive state: 0: inactiv CS=low
	p_DSPI->MCR.B.PCSIS0		= (Config->Std_CS_Mask & 1) ? 1:0;		// Peripheral Chip Select 0 inactive state: 1: inactiv CS=HIGH
  
	p_DSPI->MCR.B.MDIS			= 0b0;		// Module diable; 0:Enable DSPI CLKs; 1 Allow external logic to disable DSPI CLKs
	p_DSPI->MCR.B.DIS_TXF		= 0b0;		// Disable Receive FIFO; 0 TX FIFO enabled; 1: simplified double buffered SPI
	p_DSPI->MCR.B.DIS_RXF		= 0b0;		// Disable Receive FIFO; 0 RX FIFO enabled; 1: simplified double buffered SPI

	p_DSPI->MCR.B.CLR_TXF		= 0b0;		// Clear TX FIFO, used to flush TX_FIFO: writing a 1: Clear TX FIFO Counter
	p_DSPI->MCR.B.CLR_RXF		= 0b0;		// Clear RX FIFO, used to flush RX_FIFO: writing a 1: Clear RX FIFO Counter
	p_DSPI->MCR.B.SMPL_PT		= 0b00;		// Sample Point in modified transfers 00: rising SLK

	p_DSPI->MCR.B.PES			= 0b0;		// Parity Error Stop, 0: SPI transmission continues on error
	p_DSPI->MCR.B.HALT			= 0b1;		// 1: Stop Transfers, 0:start transfers

	// -------------------------------------------------------------------  
	//DSPI_0.CTAR[0].R 			= 0x780A7727; 		// Configure CTAR0, Clock and Transfer Attributes  //

	if (Config->FrameSize==0) return -1;
	p_DSPI->CTAR[0].B.FMSZ 	= Config->FrameSize-1;	// FMSZ:	0b0111:	8Bit (7+1) werden übertragen Frame Size
	p_DSPI->CTAR[0].B.CPOL 	= 0b0;	 	// CPOL:	0b0  	Clock Polarity 0-SCK active High
	p_DSPI->CTAR[0].B.CPHA 	= 0b0;	 	// CPHA:	0b0  	Clock Phase 0 captue data on leading edge, change on following edge
	p_DSPI->CTAR[0].B.LSBFE 	= 0b0;   	// LSBFE:	0b0     LSB first enable: 0 MSB fisrt
	
	//Delays
	if (Config->AfterSCK_Delay_Cycles < 16) {
		p_DSPI->CTAR[0].B.PASC 		= 0;  	// PASC :	0b00	After SCK Delay Prescaler 00: value is 1
		p_DSPI->CTAR[0].B.ASC 		= Config->AfterSCK_Delay_Cycles;	// ASC  :	0b0111	After Serial Clock Scaler, is the delay between the last Clk on the negation of PCS
	}
	else return -1;
	if (Config->CStoSCK_Delay_Cycles < 16) {
		p_DSPI->CTAR[0].B.PCSSCK 	= 0;  	// PCSSCK:	0b00    PCS to SCK Delay: 00 value is 1     
		p_DSPI->CTAR[0].B.CSSCK 	= Config->CStoSCK_Delay_Cycles;	// CSSCK:	0b0111	CS to SCK Delay Scaler, The CS to SCK Delay is the delay between the assertion of PCS and the first edge of SCK
	}
	else return -1;
	if (Config->DelayAfterTransfer_Cycles < 16) {
		p_DSPI->CTAR[0].B.PDT 		= 0;  	// PDT	 :	0b10	Delay after transfer Prescaler, Delay between CS signal and PCS of next frame (prescaler) 10:value is 5
		p_DSPI->CTAR[0].B.DT 		= Config->DelayAfterTransfer_Cycles;	// DT:		0b0010  Delay after transfer (time between CS at the end of the frame and the assertion of PCS of next frame)
	}
	else return -1;
	
	//BaudRate
	if (Config->Baud_Setting==DSPI_Baud15MHz) {
		p_DSPI->CTAR[0].B.DBR = 0b0;	 	// DBR: 	0b0:	Double Baud Rate:0x0 
		p_DSPI->CTAR[0].B.PBR = 0b00;  		// PBR	 :	0b01 	BaudRatePrescaler: 00 -> 2,  01 -> 3
		p_DSPI->CTAR[0].B.BR  = 0b0000;		// BR:		0b0001	BaudRateScaler; SCK baud rate= f_sys/PBR*(1+DBR)/BR, 0001: value is 4
											// 					fsys=60MHZ Peripheral 2 Settings und PBR=3,BR=4: 5MHZ Serial Port Frequency
	}
	else if (Config->Baud_Setting==DSPI_Baud5MHz) {
		p_DSPI->CTAR[0].B.DBR = 0b0;	 	// DBR: 	0b0:	Double Baud Rate:0x0 
		p_DSPI->CTAR[0].B.PBR = 0b01;  		// PBR	 :	0b01 	BaudRatePrescaler: 01 - value is 3
		p_DSPI->CTAR[0].B.BR  = 0b0001;		// BR:		0b0001	BaudRateScaler; 0000->2,0001->4; SCK baud rate= f_sys/PBR*(1+DBR)/BR, 0001: value is 4
											// 					fsys=60MHZ Peripheral 2 Settings und PBR=3,BR=4: 5MHZ Serial Port Frequency
	}
	else if (Config->Baud_Setting==DSPI_Baud2MHz) {
		p_DSPI->CTAR[0].B.DBR = 0b0;	 	// DBR: 	0b0:	Double Baud Rate:0x0 
		p_DSPI->CTAR[0].B.PBR = 0b10;	  	// PBR	 :	0b01 	BaudRatePrescaler: 01 - value is 3
		p_DSPI->CTAR[0].B.BR  = 0b0010;		// BR:		0b0001	BaudRateScaler; 0000->2,0001->4; SCK baud rate= f_sys/PBR*(1+DBR)/BR, 0001: value is 4
											// 					fsys=60MHZ Peripheral 2 Settings und PBR=3,BR=4: 5MHZ Serial Port Frequency
	}
	// -------------------------------------------------------------------  
	p_DSPI->MCR.B.HALT = 0x0;	     		// Exit HALT mode: go from STOPPED to RUNNING state, die Initialisierung nur im Halt Mode//

	// -------------------------------------------------------------------  

	// configure port pins for DSPI
	if (p_DSPI==(&DSPI_0) && Config->Port==DSPI0_PortA12) {
		SIU.PCR[12].R = 0x0103;        		// Config pad as DSPI_0 SIN input,   PA[12], FRAM DOUT 
		SIU.PCR[13].R = 0x0604;        		// Config pad as DSPI_0 SOUT output, PA[13], FRAM DIN 
		SIU.PCR[14].R = 0x0604;        		// Config pad as DSPI_0 SCK output,  PA[14], FRAM SCLK 
		SIU.PCR[15].R = 0x0604;        		// Config pad as DSPI_0 CS0 output, PA[15], FRAM CS 	
		SIU.PSMI[5].R = 0b000;		 		// select PCR[14] as SCK0_0, Fehler in Registerbeschreibung und MPC5646 Reference Manual?
		SIU.PSMI[6].R = 0b001;		 		// select PCR[15] as CS0_0
	}
	else if (p_DSPI==(&DSPI_1) && Config->Port==DSPI1_PortE4) {
		SIU.PCR[68].R = 0x0903;        		// MPC56xxB: Config pad as DSPI_1 SCK input, PE[4] //
		SIU.PSMI[7].R = 1;             		// MPC56xxB: Select PCR 68 for DSPI_1 SCK input //
		SIU.PCR[36].R = 0x0103;        		// MPC56xxB: Config pad as DSPI_1 SIN input, , PC[4] //
		SIU.PSMI[8].R = 0;             		// MPC56xxB: Select PCR 36 for DSPI_1 SIN input //
		SIU.PCR[37].R = 0x0604;        		// MPC56xxB: Config pad as DSPI_1 SOUT output, PC[5]//
		SIU.PCR[69].R = 0x0903;        		// MPC56xxB: Config pad as DSPI_1 PCS0/SS input, PE[5] //
		SIU.PSMI[9].R = 2;             		// MPC56xxB: Selec PCR 69 for DSPI_1 SS input //
	}
	else if (p_DSPI==(&DSPI_2) && Config->Port==DSPI2_PortC12) {
		SIU.PCR[44].R  = 0x0103;       		// Config pad as DSPI_2 SIN input,   PC[12], TEMP DOUT 
		SIU.PCR[45].R  = 0x0A04;       		// Config pad as DSPI_2 SOUT output, PC[13], n.u.,		AF2
		SIU.PCR[46].R  = 0x0A04;        	// Config pad as DSPI_2 SCK output,  PC[15], TEMP SCLK,	AF2 
		SIU.PSMI[10].R = 0b000;		 		// select PCR[46] as SCK_2
		SIU.PCR[47].R  = 0x0A04;        	// Config pad as DSPI_2 CS0 output, PA[14], TEMP CS,	AF2 	
		SIU.PSMI[12].R = 0b000;		 		// select PCR[47] as CS0_2
	}
	else if (p_DSPI==(&DSPI_3) && Config->Port==DSPI3_PortG2) {
		SIU.PCR[98].R  = 0x0A04;        	// Config pad as DSPI_3 SOUT output, PG[2], AF2
		SIU.PCR[99].R  = 0x0A04;        	// Config pad as DSPI_3 CS0 output,  PG[3], AF2 	
		SIU.PCR[100].R = 0x0A04;        	// Config pad as DSPI_3 SCK output,  PG[4]	AF2 
		SIU.PSMI[32].R = 0b0000;		 	// select PCR[100] as SCK_3
		SIU.PSMI[34].R = 0b0000;		 	// select PCR[99] as CS0_3
	}
	else if (p_DSPI==(&DSPI_4) && Config->Port==DSPI4_PortK9) {
		SIU.PCR[170].R = 0x0604;        	// Config pad as DSPI_4 SOUT output, AF1
		SIU.PCR[169].R = 0x0102;        	// Config pad as DSPI_4 SIN input,  
		SIU.PCR[171].R = 0x0604;        	// Config pad as DSPI_4 SCK output, AF1 
		SIU.PCR[172].R = 0x0604;        	// Config pad as DSPI_4 CS_4 output, AF1
		SIU.PSMI[35].R = 0b0011;        	// Select PCR 171 for SCK_4
		SIU.PSMI[36].R = 0b0010;        	// Select PCR 169 for SIN_4 
		SIU.PSMI[37].R = 0b0100;        	// Select PCR 172 for CS0_4 
	}
	else if (p_DSPI==(&DSPI_6) && Config->Port==DSPI6_PortG14) {
		SIU.PCR[110].R = 0x0103;        	// Config pad as DSPI_6 SIN input,   PG[14], TEMP DOUT,	 
		SIU.PCR[111].R = 0x0A04;        	// Config pad as DSPI_6 SOUT output, PG[15], n.u., 		AF2
		SIU.PCR[79].R  = 0x0E04;        	// Config pad as DSPI_6 SCK_6 output,PE[15], TEMP CS,	AF3 	
		SIU.PCR[107].R = 0x0E04;        	// Config pad as DSPI_6 CS0 output,  PG[11], TEMP SCLK,	AF3 
	}
	else return -1;
	
	return 0;
}



/*
int8_t DSPI_check_and_read(DSPI_config_t *const p_Config, uint32_t *data) {
	volatile struct DSPI_tag *p_DSPI;
	p_DSPI = p_Config->p_Modul;
	
	p_DSPI->SR.B.RFDF=1;	//clear
	if (p_DSPI->SR.B.RFDF==1) {  // Wait for Receive FIFO Drain Flag = 1 
		*data = p_DSPI->POPR.R;   // Read data received by master SPI 
		p_DSPI->SR.R = 0x90020000;    //     Clear TCF, RDRF, EOQ flags by writing 1
		return 1;	//Nachricht empfangen
	}
	else return 0; //keine Nachricht
}
*/



int8_t DSPI_push(DSPI_config_t *const p_Config, uint16_t data, uint8_t isEOQ)
{
	volatile struct DSPI_tag *p_DSPI;
	uint32_t push_tmp = 0;
	
	p_DSPI = p_Config->p_Modul;
	
	p_DSPI->SR.B.TFFF = 1;	//TFFF zurücksetzen
	if ( ! p_DSPI->SR.B.TFFF ) return -1;	//Fifo voll?
	
	if (isEOQ) {	//Letztes Byte/Wort des Frames?
		push_tmp |= 0x08000000;	//EOQ End Of Queue
	}
	else {
	 	if (p_Config->CS_Cont==CS_Cont_ON)
 			push_tmp |= 0x80000000;
	}
	push_tmp |= (p_Config->Std_CS_Mask << 16); //ChipSelect
	push_tmp |= data;
	
	p_DSPI->PUSHR.R = push_tmp;
	
	return 0;
	
	/*	DSPI_0.PUSHR.B.CONT		= 0;							// Cont. CS enable between TX (0: CS is switch into idle after TX)
	DSPI_0.PUSHR.B.CTAS		= 0b000;							// No. of CTAR Reg. selected
	DSPI_0.PUSHR.B.EOQ		= 0b1;								// End of Queue (1: Last Data to be TX)
	DSPI_0.PUSHR.B.CTCNT	= 0b0;								// Clear TX Counter (0: do not clear counter)
	DSPI_0.PUSHR.B.PE		= 0b0;								// Parity enable (0: no parity)
	DSPI_0.PUSHR.B.PP		= 0b0;								// Parity Polarity (0: even)
	// ::2
	DSPI_0.PUSHR.B.PCS5		= 0b0;								// 1: Assert peripheral Chip select
	DSPI_0.PUSHR.B.PCS4		= 0b0;								// 1: Assert peripheral Chip select
	DSPI_0.PUSHR.B.PCS3		= 0b0;								// 1: Assert peripheral Chip select
	DSPI_0.PUSHR.B.PCS2		= 0b0;								// 1: Assert peripheral Chip select
	DSPI_0.PUSHR.B.PCS1		= 0b0;								// 1: Assert peripheral Chip select
	DSPI_0.PUSHR.B.PCS0		= 0b1;								// 1: Assert peripheral Chip select
	DSPI_0.PUSHR.B.TXDATA	= TxDataDAC;						// TX Data to be transmitted
*/
}



int8_t DSPI_pop(DSPI_config_t *const p_Config, volatile uint16_t *const data)
{
	volatile struct DSPI_tag *p_DSPI;
	p_DSPI = p_Config->p_Modul;
	
	p_DSPI->SR.B.RFDF=1;	//clear
	if ( ! p_DSPI->SR.B.RFDF ) return -1;	//Fifo leer?
	*data = (vuint16_t)(p_DSPI->POPR.R & 0xFFFF);
	p_DSPI->SR.B.RFDF = 1;	//Drain-Flag zurücksetzen
	return 0;
}



int8_t DSPI_init_Tx(DSPI_config_t *const p_Config)
{
	volatile struct DSPI_tag *p_DSPI;
	p_DSPI = p_Config->p_Modul;
	if ( p_DSPI->SR.B.TXCTR != 0 ) return -1;
	p_DSPI->SR.B.EOQF = 1;	//EOQ-Flag löschen
	p_DSPI->SR.B.TCF = 1;	//EOQ-Flag löschen
	return 0;
}



int8_t DSPI_Clear_RxFifo(DSPI_config_t *const p_Config)
{
	volatile struct DSPI_tag *p_DSPI;
	uint32_t dummy;
	p_DSPI = p_Config->p_Modul;
	while (p_DSPI->SR.B.RXCTR != 0) {
		dummy = p_DSPI->POPR.R;
	}
	p_DSPI->SR.B.RFDF = 1;	//Drain-Flag zurücksetzen
	/*
	if (p_DSPI->SR.B.RXCTR != 0) {
		p_DSPI->MCR.B.CLR_RXF = 1;
		p_DSPI->SR.B.RFDF = 1;	//Drain-Flag zurücksetzen
		return 1;	//Fifo gelöscht
	}*/
	
	return 0; //keine Nachricht im Fifo
}