Master_BMS/BMS Master/Sources/Device.c

#include "BMS_Master.h"



extern uint32_t __IVPR_VALUE; /* Interrupt Vector Prefix value from link file*/
extern uint32_t IntcIsrVectorTable[];


#define CHIPVERSION	F1



void init_Device()
{
	//--INIT-----------------------------------------------
	// (1) Disable Watchdog --------------------------
	disableWatchdog(); /* Disable watchdog */
	// -----------------------------------------------

	INTC_InstallINTCInterruptHandler(&ISR_Timer_OS,59,10);	//irq(PIT0) = 59
	INTC_InitINTCInterrupts();
	Asm_initIrqVectors();
    INTC.PSR[4].R = 2;		          /* Software interrupt 4 IRQ priority = 2 */
	INTC.CPR_PRC0.B.PRI = 1;          /* Single Core: Lower INTC's current priority */
		
	/* (2) - Configure modes and activate all clock for all peripherals      */ 
	initMODE();

	/* (3) - Configure system clock dividers for 120Mhz Fsys                 */
	CGM.Z0_DCR.B.DIV = 0x1;       /* Z0 clock divider to divide by 2        */
	CGM.FLASH_DCR.B.DIV = 0x1;    /* Flash register interface /2 (default)  */
	ECSM.MUDCR.B.RAM_WS=0x1;      /* RAM Wait states to divide by 2         */

	/* (4) - Set system clock to 120MHz based on 40Mhz XTAL                  */
	setPLL();                     /* Also enables CLKOUT On PA[0]           */     

	initINTC();
}



/* ----------------------------- */
/* Initialize Modes              */
/* ----------------------------- */
void initMODE()
{            
    ME.MER.R = 0x000025FF;          /* Enable all modes                     */
    ME.RUNPC[0].R = 0x000000FE; 	/* Enable all peripherals in all modes  */
    
   /* Enable system clock for all peripherals assuming 120MHz system clock  */
    CGM.SC_DC0.R = 0x83;          	/* Max 32MHz. Closest is 30MHz, Div+1=4 */
    CGM.SC_DC1.R = 0x81;          	/* Max 64MHz. Closest is 60MHz, Div+1=2 */
    CGM.SC_DC2.R = 0x81;          	/* Max 64MHz. Closest is 60MHz, Div+1=2 */

    /* Re-enter DRUN mode to update the clock configuration                 */
    ME.MCTL.R = 0x30005AF0;         /* DRUN Mode & Key                      */
    ME.MCTL.R = 0x3000A50F;         /* DRUN Mode & Key                      */
    while (ME.IS.B.I_MTC != 1) {}   /* Wait Until transition completed      */
    ME.IS.B.I_MTC = 1;              /* Clear flag                           */   
   
    //CAN 
    ME.RUNPC[1].R = 0x00000018; 	/* Peri. Cfg. 1 settings: only run in DRUN & RUN0 mode */
    ME.PCTL[16].R = 0x01;           /* MPC56xxB/P/S FlexCAN0:select ME.RUNPC[1] */	
//  ME.PCTL[17].R = 0x01;           /* MPC56xxB/S FlexCAN1:  select ME.RUNPC[1] */	
    ME.PCTL[68].R = 0x01;           /* MPC56xxB/S SIUL:      select ME.RUNPC[1] */	
    ME.PCTL[91].R = 0x01;           /* MPC56xxB/S RTC/API:   select ME.RUNPC[1] */	
    ME.PCTL[92].R = 0x01;           /* MPC56xxB/S PIT_RTI:   select ME.RUNPC[1] */	
    ME.PCTL[4].R = 0x01;           	/* MPC56xxB/S DSPI0:     select ME.RUNPC[1] */	
    ME.PCTL[5].R = 0x01;           	/* MPC56xxB/S DSPI1:     select ME.RUNPC[1] */	
    ME.PCTL[48].R = 0x01;           /* MPC56xxB/S LINFLEX0:  select ME.RUNPC[1] */	
    ME.PCTL[49].R = 0x01;           /* MPC56xxB/S LINFLEX1:  select ME.RUNPC[1] */	
}



void init_Mode_and_Clock()
{
	//--PLL--
	//Nur einstellen, wenn PLL nicht Sysclk
	//F_vco = F_xtal * NDIV/(IDIF+1) = 256...512
	//F_PLL_outclk = F_vco / 2^(ODIF+1)
	CGM.FMPLL_CR.B.IDF= 3; /* Divide by 4 */
	CGM.FMPLL_CR.B.ODF= 1; /* Divide by 4 */
	CGM.FMPLL_CR.B.NDIV=48; /* Multiply 48 */
	
	/* Switch on external osc in DRUN mode */
	ME.DRUN.B.FXOSC0ON=1;
	//Set PLL to Soure in DRUN
	ME.DRUN.B.SYSCLK=4;
	
	ME.MCTL.R = 0x30005AF0; /* Mode & Key */
	ME.MCTL.R = 0x3000A50F; /* Mode & Key inverted */
	while(ME.GS.B.S_MTRANS == 1) {} /* Wait for mode transition complete */
	/* Error trap - if current mode is not DRUM (eg safe mode), then loop */
	while(ME.GS.B.S_CURRENTMODE != 3) {}

	/* Wait for external OSC to stabilize */
	while(ME.GS.B.S_FXOSC != 1) {}

	// wait for PLL to lock
	while(CGM.FMPLL_CR.B.S_LOCK==0) {}
	
	/* Enable CLKOUT pin so clock frequency can be verified */
	CGM.OC_EN.B.EN=1; 		/* Enable Output clock */
	CGM.OCDS_SC.R =0x23; 	/* And seclect output as system clock / 4 */
	SIU.PCR[0].R = 0x0A04; 	/* PA0 ALT2 function (Clkout), MAX SRC */
}



/* ----------------------------- */
/* PLL to 120Mhz (40Mhz xtal) */
/* ----------------------------- */
void setPLL()
{
	/* Note - in example code below the flow is: */
	/* Switch on osc, change mode and wait for osc ON */
	/* Configure and enable PLL, change mode and wait for PLL to lock */
	/* Set clock source as PLL, change mode and check clock is PLL */
	/* */

	/* However, do not actually have to do all 3 mode changes. Can */
	/* switch on osc, enable PLL and Set PLL as clock source THEN do a */
	/* single mode change. The ME module must be smart enough to look */
	/* at which bits are set and see if it's a valid combination of */
	/* bits. However, if there is an issue, there is no way of seeing */
	/* what caused the problem! */
#ifdef EVALBOARD
	/* Switch on external osc in DRUN mode */
	ME.DRUN.B.FXOSC0ON=1;
#else
	//MasterBoard
	CGM.FXOSC_CTL.B.OSCBYP=1;
	ME.DRUN.B.FXOSC0ON=1;
#endif
	/* Re-Enter DRUN mode (mode=0x3) to activate change */
	ME.MCTL.R = 0x30005AF0; /* Mode & Key */
	ME.MCTL.R = 0x3000A50F; /* Mode & Key inverted */
	while(ME.GS.B.S_MTRANS == 1) {} /* Wait for mode transition complete */

	/* Error trap - if current mode is not DRUM (eg in safe mode), then loop */
	while(ME.GS.B.S_CURRENTMODE != 3) {}

	/* Wait for external OSC to stabilize */
	while(ME.GS.B.S_FXOSC != 1) {}

	/* Select External OSC as the FMPLL Reference Clock Source */
#if CHIPVERSION == F1
	CGM.AC0_SC.B.SELCTL = 0x0;
#elif CHIPVERSION == F0
	CGM.AC0_SC.B.SELCTL = 0x1;
#else
	#error Device.c: Keine gültige Cipversion ausgewählt
#endif

	/* Configure PLL for 120MHz with 40MHz xtal */
	/* PLL frequency = (40 * NDIV) / (IDF * ODF) */
	/* VCO (PLL * ODF) must be between 256 and 512MHz */
	/* */
	/* For 120Mhz Output: */

	/* ODF deliviers are 2, 4, 8, 16. /4 gives VCO of 480 (in range) */
	/* With ODF = 2, NDIV = 12xIDF. Chose IDF =5, therefore NDIV = 60 */
	CGM.FMPLL_CR.B.IDF=0x4; /* Divide by 5 */
	CGM.FMPLL_CR.B.ODF=0x1; /* Divide by 4 */
	CGM.FMPLL_CR.B.NDIV=60; /* Divide by 60 */
	/* Enable PLL in DRUN mode. */
	ME.DRUN.B.FMPLLON = 1;

	/* Re-Enter DRUN mode (mode=0x3) to activate change */
	ME.MCTL.R = 0x30005AF0; /* Mode & Key */
	ME.MCTL.R = 0x3000A50F; /* Mode & Key inverted */

	while(ME.GS.B.S_MTRANS == 1) {} /* Wait for mode transition complete */
	/* Error trap - if current mode is not DRUM (eg safe mode), then loop */
	while(ME.GS.B.S_CURRENTMODE != 3) {}
	/* wait for PLL to lock (will not lock until re-enter DRUN mode */
	while(CGM.FMPLL_CR.B.S_LOCK==0) {}
	/* Finally set system clock to be PLL in DRUN mode */
	ME.DRUN.B.SYSCLK=0x4;

	/* Re-Enter DRUN mode (mode=0x3) to activate change */
	// Application Code
	// Getting started with the MPC564xB/C Microcontroller, Rev. 0, 12/2010
	// 20 Freescale Semiconductor, Inc.
	ME.MCTL.R = 0x30005AF0; /* Mode & Key */
	ME.MCTL.R = 0x3000A50F; /* Mode & Key inverted */
	while(ME.GS.B.S_MTRANS == 1) {} /* Wait for mode transition complete */

	/* Error trap - if current mode is not DRUM (eg safe mode), then loop */
	while(ME.GS.B.S_CURRENTMODE != 3) {}

	/* Final check - ensure ME_GS reports clock as system PLL (0x4) */
	while(ME.GS.B.S_SYSCLK != 4) {} /* fail if stuck here */

	/* Enable CLKOUT pin so clock frequency can be verified */
	CGM.OC_EN.B.EN=1; 		/* Enable Output clock */
	CGM.OCDS_SC.R =0x23; 	/* And seclect output as system clock / 4 */
	SIU.PCR[0].R = 0x0A04; 	/* PA0 ALT2 function (Clkout), MAX SRC */
}



void disableWatchdog()
{
  SWT.SR.R = 0x0000c520;     /* Write keys to clear soft lock bit */
  SWT.SR.R = 0x0000d928; 
  SWT.CR.R = 0x8000010A;     /* Clear watchdog enable (WEN) */
}        



void initINTC()
{	
  INTC.MCR.B.HVEN_PRC0 = 1;       /* 0 -> SW vector mode */
  INTC.MCR.B.VTES_PRC0 = 0;       /* Single core: Use default vector table 4B offsets */
  INTC.IACKR_PRC0.R = 2;    /* MPC555x: INTC ISR table base */
  INTC.PSR[59].R = 4;           /* PIT 0 interrupt vector with priority 1 */
  INTC.PSR[0].R = 3;		/* Software interrupt 0 IRQ priority = 2 */
  INTC.PSR[1].R = 2;		/* Software interrupt 1 IRQ priority = 2 */
  INTC.PSR[2].R = 1;		/* Software interrupt 2 IRQ priority = 2 */
}



void enableIrq()
{
  INTC.CPR_PRC0.B.PRI = 0;          /* Single Core: Lower INTC's current priority */
  asm(" wrteei 1");	    	   /* Enable external interrupts */
}



void Asm_initIrqVectors( void )
{
  asm(" lis r3, __IVPR_VALUE@h");   /* IVPR value is passed from link file */
  asm(" ori r3, r3, __IVPR_VALUE@l"); 
  asm(" mtivpr  r3");
  asm(" li r3, 0x40");  
  asm(" mtivor4 r3");  							 
}