Master_BMS/BMS Master/Sources/FRAM.c

// ----------------------------------------------------------------------------
// FRAM.c - 
// ----------------------------------------------------------------------------
// Beschreibung:	FRAM mit SPI-IF
//
// Revision:		02. Juli 2012, neu	Maurer, IPE
//					19. Juli 2012, +Polling-Betrieb der FSM
// ----------------------------------------------------------------------------

#include "BMS_Master.h"



FramStatus_t Fram_S;


static const FramStatus_t Fram_S_INIT = {Fram_Idle,NoTask,0,0,(uint8_t*)0,0,0,0};



static int8_t FRAM_FSM_update(uint8_t tick);
static int8_t FRAM_get_SuccessState();


DSPI_config_t FRAM_SPI_conf = {
	&DSPI_0,
	DSPI_Master,
	8,	//FrameSize
	DSPI_ClassicFormat,
	DSPI_Baud2MHz,
	2,	//uint8_t CStoSCK_Delay_Cycles;	//nur MasterMode;
	2,	//uint8_t AfterSCK_Delay_Cycles;	//nur MasterMode;
	0,	//uint8_t DelayAfterTransfer_Cycles;	//nur MasterMode;
	1,
	CS_Cont_ON,	//enum{CS_Cont_ON, CS_Cont_OFF};
	DSPI0_PortA12
} ;


//==================================================================================================
//API





int8_t FRAM_init(void)
{
	int8_t ret;
	ret = DSPI_init(&FRAM_SPI_conf);
	
//	SIU.PCR[153].R	= 0x0302;	// FRAM_WP;act Low		PJ[9] Output enable, input enable, Weak PU/PD enable, Weak PD selected
//	SIU.PCR[154].R	= 0x0303;	// FRAM_HOLD;act. Low	PJ[10] Output enable, input enable, Weak PU/PD enable, Weak PU selected
	SIU.PCR[153].B.OBE = 1;	// FRAM_WP;act Low		PJ[9] Output enable,
	SIU.PCR[154].B.OBE = 1;	// FRAM_HOLD;act. Low	PJ[10] Output enable
	
	SET_OUTPIN(153);		// set PJ[9],	/WP = 1 (switch off HW Write Protection of FRAM)
	SET_OUTPIN(154);		// set PJ[10],	/hold = 1 (do not hold the FRAM)
	
	Fram_S = Fram_S_INIT;
	return ret;
}



int8_t FRAM_update(uint8_t tick)
{ 
	return FRAM_FSM_update(tick);
}



int8_t FRAM_trigger_write(const vuint16_t Addr, vuint8_t *const data, const vuint8_t num_data)
{
	if (num_data < 1) return -1;
	if (Fram_S.FsmState != Fram_Idle) return -2;
//	if (Fram_S.FramTest_state != 0) return -3;
	
	Fram_S.TaskTrigger = RamWrite;
	Fram_S.Addr = Addr;
	Fram_S.datastart = data;
	Fram_S.num_data = num_data;
		
	return 0;
}



int8_t FRAM_trigger_read(const vuint16_t Addr, vuint8_t *const data, vuint8_t num_data)
{
	if (num_data < 1) return -1;
	if (Fram_S.FsmState != Fram_Idle) return -2;
//	if (Fram_S.FramTest_state != 0) return -3;

	Fram_S.TaskTrigger = RamRead;
	Fram_S.Addr = Addr;
	Fram_S.datastart = data;
	Fram_S.num_data = num_data;
		
	return 0;
}



int8_t FRAM_trigger_Test()
{
	if (Fram_S.FsmState != Fram_Idle) return -1;
	Fram_S.TaskTrigger = RamTest;	
	return 0;
}



int8_t FRAM_Test_update()
{
	#define NUM_DATA	10
	#define DATA_1		0xCC
	#define DATA_2		0x33
	static vuint8_t data[NUM_DATA];
	uint8_t i = 0;
		
	switch (Fram_S.FramTest_state)	{
		case 0:
			if (Fram_S.TaskTrigger == RamTest) {
				Fram_S.TaskTrigger = NoTask;
				for (i=0;i<NUM_DATA;i++) data[i] = DATA_1;
				if (FRAM_trigger_write(0, &data[0], NUM_DATA) < 0) return -1;
				Fram_S.FramTest_state = 1;
			}
			break;
		case 1:
			if (FRAM_get_SuccessState() < 0) {
				Fram_S.FramTest_state = 0;
				return -2;
			}
			if (FRAM_get_SuccessState() > 0) {
				Fram_S.FramTest_state = 0;
				for (i=0;i<NUM_DATA;i++) data[i] = 0;
				if (FRAM_trigger_read(0, data, NUM_DATA) < 0) return -3;
				Fram_S.FramTest_state = 2;
			}
			break;
		case 2:
			if (FRAM_get_SuccessState() < 0) {
				Fram_S.FramTest_state = 0;
				return -4;
			}
			if (FRAM_get_SuccessState() > 0) {
				Fram_S.FramTest_state = 0;
				for (i=0;i<NUM_DATA;i++) if ( data[i] != DATA_1 ) return -5;
				for (i=0;i<NUM_DATA;i++) data[i] = DATA_2;
				if (FRAM_trigger_write(0, &data[0], NUM_DATA) < 0) return -6;
				Fram_S.FramTest_state = 3;
			}
			break;
		case 3:
			if (FRAM_get_SuccessState() < 0) {
				Fram_S.FramTest_state = 0;
				return -7;
			}
			if (FRAM_get_SuccessState() > 0) {
				for (i=0;i<NUM_DATA;i++) data[i] = 0;
				FRAM_trigger_read(0, &data[0], NUM_DATA);
				Fram_S.FramTest_state += 1;
			}
			break;
		case 4:
			if (FRAM_get_SuccessState() < 0) {
				Fram_S.FramTest_state = 0;
				return -8;
			}
			if (FRAM_get_SuccessState() > 0) {
				Fram_S.FramTest_state = 0;
				for (i=0;i<NUM_DATA;i++) if (data[i] != DATA_2) return -9;
				return 1;	//Test erfolgreich
			}
			break;
	}
	return 0;
	#undef NUM_DATA
	#undef DATA_1
	#undef DATA_2
}



//==================================================================================
static int8_t FRAM_push(uint16_t data, uint8_t isEOQ)
{
	return DSPI_push(&FRAM_SPI_conf, data, isEOQ);
}



static int8_t FRAM_pop(vuint16_t *dataptr)
{
	return DSPI_pop(&FRAM_SPI_conf, dataptr);
}



//-----------------------------------------------------------------------
typedef enum {noEOQ=0, withEOQ} EOQbool_t;

typedef struct {
	vuint8_t *datastart;
	uint16_t i_data;
	uint16_t i_read;
	uint16_t i_dummy;
	uint16_t num_data;
	EOQbool_t EOQbool;
	uint8_t busy;
} Seqnce_Status_t;



static volatile Seqnce_Status_t Seqnce_S;



static int8_t FRAM_Seqnce_init(){
	Seqnce_S.datastart = 0;
	Seqnce_S.num_data = 0;
	Seqnce_S.i_data = 0;
	Seqnce_S.i_read = 0;
	Seqnce_S.i_dummy = 0;
	Seqnce_S.EOQbool = noEOQ;
	Seqnce_S.busy = 0;
	return 0;
}



static int8_t FRAM_Seqnce_try_load(vuint8_t *data, uint16_t num_data, EOQbool_t EOQbool)
{
	if (Seqnce_S.busy) return -1;
	Seqnce_S.datastart = data;
	Seqnce_S.num_data = num_data;
	Seqnce_S.i_data = 0;
	Seqnce_S.i_read = 0;
	Seqnce_S.EOQbool = EOQbool;
	Seqnce_S.busy = 1;
	return 0;
}



static int8_t FRAM_get_SuccessState()
{
	if (Fram_S.TaskTrigger == NoTask) {
		if (Fram_S.Flags.B.FSM_TO) return -1;
		if (Fram_S.Flags.B.JobFinished) return 1;
	}
	return 0;
}



static int8_t FRAM_Seqnce_try_push()
{
	uint16_t cnt_sent = 0;
	uint8_t  isEOQ    = 0;
	
	while (Seqnce_S.i_data < Seqnce_S.num_data)    // transmit still running
	{
		if ( Seqnce_S.i_data == (Seqnce_S.num_data-1) && Seqnce_S.EOQbool==withEOQ ) // last Byte transmit
		{
			isEOQ = 1;
		}
		
		if ( FRAM_push((uint16_t)(Seqnce_S.datastart[Seqnce_S.i_data]) & 0xFF, isEOQ) < 0 ) 
		{
			if ( cnt_sent==0 ) 
				return -1; //nothing sent
			else 
				return 0;	//sent but not finished
		}
		else 
		{
			cnt_sent++;
			Seqnce_S.i_data++;
		}
	}
	//end of data
	Seqnce_S.busy = 0;
	return 1;	//1 = finished
}



static int8_t FRAM_Seqnce_load_forDummies(vuint8_t *datastart,uint16_t num_data)
{
//	if (Seqnce_S.busy) return -1;
	Seqnce_S.datastart = datastart;
	Seqnce_S.num_data = num_data;
	Seqnce_S.i_data = 0;
	Seqnce_S.i_read = 0;
	Seqnce_S.i_dummy = 0;
	Seqnce_S.busy = 1;
	return 0;
}



static int8_t FRAM_Seqnce_try_pushDummies()
{
	uint16_t cnt_sent = 0;
	uint8_t  isEOQ    = 0;
	
	while (Seqnce_S.i_data < Seqnce_S.num_data)   // while transmit still running
	{
	    if ( Seqnce_S.i_data == (Seqnce_S.num_data-1) ) // last Byte transmit?
	    {
			isEOQ = 1;
		}
		
	    if ( FRAM_push(Seqnce_S.i_data, isEOQ) < 0 ) 
		{
			return 0;	//sent but not finished
		}
		else 
		{
			Seqnce_S.i_data++;
			cnt_sent++;
			if (cnt_sent>=4) 
				return 0; //nothing sent
		}
	}
	Seqnce_S.busy = 0;
	return 1;	//1 = finished
}	



static int8_t FRAM_Seqnce_try_pop()
{
	vuint16_t data_tmp = 0;
	
	while (Seqnce_S.i_dummy < Fram_S.n_RxDummies) 
	{
		if ( FRAM_pop(&data_tmp) < 0 ) 
			return 0;    // Error: Fifo empty
		else 
			Seqnce_S.i_dummy++;
	}
	
	data_tmp = 4;
	while (Seqnce_S.i_read < Seqnce_S.num_data) 
	{
		if ( FRAM_pop(&data_tmp) < 0 )
			return 0;           // Error: Fifo empty
		else 
		{
			Seqnce_S.datastart[Seqnce_S.i_read] = (vuint8_t)(data_tmp&0xFF);
			Seqnce_S.i_read++;
		}
	}
	//end of data
	return 1;	//1 = finished
}



//-----------------------------------------------------------------------
static int8_t FRAM_checkTimeOut(uint16_t Cnt, uint16_t TO_Value)
{	
	if (Cnt >= TO_Value) {
		FRAM_init();
		Fram_S.Flags.B.FSM_TO = 1;
		return -1;
	}
	return 0;
}



//FRAM FSM
static int8_t FRAM_FSM_update(uint8_t tick)
{
	#define FSM_TIMEOUT	6
	static uint8_t OPCSeq[3];
	static uint16_t StateTimeoutCnt = 0;
	
	if (tick == 1) StateTimeoutCnt += 1;
	switch (Fram_S.FsmState)	{
		case Fram_Idle:
			if (Fram_S.TaskTrigger == RamWrite) {
				//PushOPCs
				//if (Fram_S.num_data == 0) return -1;
				FRAM_SPI_conf.CS_Cont = CS_Cont_OFF;	//Select geht nach dem Byte aus
				//Write_Enable vor jedem Schreiben auf Speicher
				FRAM_push(WREN_OPC,0);
				//Write-Befehl
				FRAM_SPI_conf.CS_Cont = CS_Cont_ON;	//CS bleibt zw. den Bytes aktiv
				OPCSeq[0] = WRITE_OPC;
					//2Byte Adresse (= Adr. des 1.Databytes) 0..7FFFh
				OPCSeq[1] = (uint8_t)(Fram_S.Addr>>8) & 0x7F;
				OPCSeq[2] = (uint8_t)Fram_S.Addr & 0xFF;
				if (FRAM_Seqnce_try_load(OPCSeq,3,noEOQ) >= 0 ) {
					Fram_S.Flags.R = 0;
					StateTimeoutCnt = 0;
					Fram_S.FsmState = Fram_Write_1;
					Fram_S.TaskTrigger = NoTask;
				}
			}
			else if (Fram_S.TaskTrigger == RamRead) {
				if (Fram_S.num_data == 0) break;
				FRAM_SPI_conf.CS_Cont = CS_Cont_ON;
				OPCSeq[0] = READ_OPC;
					//2Byte Adresse (= Adr. des 1.Databytes) 0..7FFFh
				OPCSeq[1] = (uint8_t)(Fram_S.Addr>>8) & 0x7F;
				OPCSeq[2] = (uint8_t)Fram_S.Addr & 0xFF;
				DSPI_Clear_RxFifo(&FRAM_SPI_conf);
				if (FRAM_Seqnce_try_load(OPCSeq,3,noEOQ) >= 0 ) {
					DSPI_Clear_RxFifo(&FRAM_SPI_conf);
					StateTimeoutCnt = 0;
					Fram_S.Flags.R = 0;
					Fram_S.n_RxDummies = 3;
					Fram_S.FsmState = Fram_Read_1;
					Fram_S.TaskTrigger = NoTask;
				}
			}
			break;
		//auf den Ram Schreiben
		case Fram_Write_1:
			if (FRAM_checkTimeOut(StateTimeoutCnt,FSM_TIMEOUT) < 0) return -1;
			if (FRAM_Seqnce_try_push() == 1 ) {	//finished
				FRAM_Seqnce_try_load(Fram_S.datastart,Fram_S.num_data,withEOQ);
				StateTimeoutCnt = 0;
				Fram_S.FsmState = Fram_Write_2;
			}
			break;
		case Fram_Write_2:
			if (FRAM_checkTimeOut(StateTimeoutCnt,FSM_TIMEOUT) < 0) return -2;
			if (FRAM_Seqnce_try_push() == 1 ) {	//finished
				StateTimeoutCnt = 0;
				Fram_S.FsmState = Fram_Write_3;
			}
			break;
		case Fram_Write_3:
		{
			volatile struct DSPI_tag *p_DSPI = FRAM_SPI_conf.p_Modul;
			if (FRAM_checkTimeOut(StateTimeoutCnt,FSM_TIMEOUT) < 0) return -3;
			if (p_DSPI->SR.B.EOQF == 1) {
				p_DSPI->SR.B.EOQF = 1;
				Fram_S.Flags.B.JobFinished = 1;
				StateTimeoutCnt = 0;
				Fram_S.FsmState = Fram_Idle;
			}
			break;
		}
		//vom Ram lesen
		case Fram_Read_1:
			if (FRAM_checkTimeOut(StateTimeoutCnt,FSM_TIMEOUT) < 0) return -4;
			if (FRAM_Seqnce_try_push() == 1 ) {	//finished?
				FRAM_Seqnce_load_forDummies(Fram_S.datastart,Fram_S.num_data);
				StateTimeoutCnt = 0;
				Fram_S.FsmState = Fram_Read_2;
			}
			break;
		case Fram_Read_2:
			if (FRAM_checkTimeOut(StateTimeoutCnt,FSM_TIMEOUT) < 0) return -6;
			FRAM_Seqnce_try_pop();
			if (FRAM_Seqnce_try_pushDummies() == 1 ) {	//finished
				StateTimeoutCnt = 0;
				Fram_S.FsmState = Fram_Read_3;
			}
			break;

		case Fram_Read_3:
		{
			volatile struct DSPI_tag *p_DSPI = FRAM_SPI_conf.p_Modul;
			if (FRAM_checkTimeOut(StateTimeoutCnt,FSM_TIMEOUT) < 0) {
//				while (1) {}
				return -6;
			}
			if (FRAM_Seqnce_try_pop()==1 ) {// && p_DSPI->SR.B.EOQF == 1) {
				p_DSPI->SR.B.EOQF = 1;
				StateTimeoutCnt = 0;
				Fram_S.Flags.B.JobFinished = 1;
				Fram_S.FsmState = Fram_Idle;
			}
			break;
		}
			
	}
	return 0;
	#undef FSM_TIMEOUT
}