Master_BMS/BMS Master/Project_Settings/Linker_Files/MPC5646C_FLASH.lcf

/* Internal FLASH linker command file for MPC5646C                          */
/*                                                                          */
/*               3MB Flash, 256KB SRAM                                      */
/*                                                                          */
/* Intended to be used for the stationary example project.                  */
/* This LCF should be used in single core projects.                         */
/*                                                                          */
/* VERSION: 1.1                                                             */

MEMORY
{
	/* FLASH: 0x00000000 - 0x0002FFFFF */
	/* Fixed location required for RCHW, program entry point and CSE array length */
    resetvector:           org = 0x00000000,   len = 0x00000010
    
    /* Contains initializations from __ppc_eabi_init.c,
     MPC56xx_HWInit.c, MPC56xx_init_*.c and the entry point (__startup).
     Should be 4K of since the system automatically creates a default TLB entry
     from the start of the entry point specified in RCHW.  
     */
	init:				   org = 0x00000010,   len = 0x00000FF0 /* 4K */
	
	/* 64K gap required to align the exception handlers.*/
	 	
    /* Contains interrupt branch tables for both z4 core and INTC module
     and the ISR handlers code. Note, the gap is required since the vector
     base address field of Z4 IVPR is defined within the range [0:15], the
     INTC branch tables must be loaded at an address aligned to 64K boundary.
     */    
    exception_handlers_p0: org = 0x00010000,   len = 0x0030000 /* 192K */
    
    /* Space allocated for user code and device initialization.
    ROM Image address should be set with the start address of this
    segment in order to instruct the runtime to initialize the
    static variables. All the section above are ignored for this action. 
    Please see -romaddr linker option.*/
    internal_flash:        org = 0x00040000,   len = 0x002C0000 /* ~2800K */
    
    
    /* SRAM: 0x40000000 - 0x40003FFFF */
    internal_ram:          org = 0x40000000,   len = 0x00030000
    heap  :                org = 0x40030000,   len = 0x00008000
    stack :                org = 0x40038000,   len = 0x00008000
}

/* This will ensure the rchw and reset vector are not stripped by the linker */
FORCEACTIVE { "bam_rchw" "bam_resetvector"}

SECTIONS
{
    .__bam_bootarea LOAD (ADDR(resetvector)): {} > resetvector

    /* Section used for initialization code: __ppc_eabi_init.c,
     MPC56xx_HWInit.c, MPC56xx_init_*.c and the entry point (__startup).
     */
    GROUP  : {
      .init LOAD (ADDR(init)) : {}
      .init_vle (VLECODE) LOAD (_e_init) : {
        *(.init)
        *(.init_vle)
      }
    } > init

   /* Note: _e_ prefix enables load after END of that specified section */
   GROUP : {
   	  /* Special section for INTC branch table required in hardware mode.
   	  Place the .intc_hw_branch_table_p0 section first in order to used both core and INTC
      tables. The intc_hw_branch_table should contain entries aligned to 16 bytes.
      */
      .intc_hw_branch_table_p0  LOAD (ADDR(exception_handlers_p0)) ALIGN (0x10) : {}
 
      /* Because the Z4 IVORx are settable the IVOR branch table can be placed
      after the INTC HW table.*/
      .ivor_branch_table_p0 (VLECODE) LOAD (_e_intc_hw_branch_table_p0) ALIGN (0x10) : {}
      
      /* ISR handlers code. */
      .__exception_handlers_p0 (VLECODE) LOAD (_e_ivor_branch_table_p0) : {}
   } > exception_handlers_p0

    GROUP  : {

      .text : {} 
      .text_vle (VLECODE) : {
         *(.text)
         *(.text_vle)
       }
       
       .rodata (CONST) : {
         *(.rdata)
         *(.rodata)
       }
       
       .ctors : {}
       .dtors : {}
       extab : {}
       extabindex : {}
    } > internal_flash

    GROUP : {
    	/* Used in INTC SW mode to store the interrupt handlers array. Should be aligned to 4K. */
       .__uninitialized_intc_handlertable ALIGN(0x1000) : {}
       .data   : {}
       .sdata  : {}
       .sbss   : {}
       .sdata2 : {}
       .sbss2  : {}
       .bss    : {}
    } > internal_ram
}

/* Freescale CodeWarrior compiler address designations */

_stack_addr = ADDR(stack)+SIZEOF(stack);
_stack_end  = ADDR(stack);
_heap_addr  = ADDR(heap);
_heap_end   = ADDR(heap)+SIZEOF(heap);

/* If INTC HW mode is used it represents the vector base address to set
IVPR and the location of intc_hw_branch_table_p0 section. The EXCEPTION_HANDLERS
will point to the IVOR branch table.
*/
__IVPR_VALUE = ADDR(exception_handlers_p0);

/* IVOR branch table location. Used in Exceptions.c */
EXCEPTION_HANDLERS = ADDR(.ivor_branch_table_p0);

/* L2 SRAM Location (used for L2 SRAM initialization) */
L2SRAM_LOCATION = ADDR(internal_ram);

/* How many writes with stmw, 128 bytes each, are needed to cover
   the whole L2SRAM (used for L2 SRAM initialization) */
L2SRAM_CNT = 0x40000 / 128;