Master_BMS/BMS Master/Project_Settings/Linker_Files/MPC5646C_RAM.lcf

/* Internal RAM linker command file for MPC5646C                            */
/*                                                                          */
/*               3MB Flash, 256KB SRAM                                      */
/*                                                                          */
/* Intended to be used for the stationary example project.                  */
/* This LCF should be used in single core projects.                         */
/*                                                                          */
/* VERSION: 1.1                                                             */

MEMORY
{
    /* SRAM: 0x40000000 - 0x4003FFFF */
    
    /* Contains interrupt branch tables for both Z4 core and INTC module
     and the ISR handlers code. Note, since the vector base address field
     of Z4 IVPR is defined within the range [0:15] the branch tables must
     be loaded at an address aligned to 64K boundary, for eg. 0x4000_0000.
     */    
    exception_handlers_p0: org = 0x40000000,   len = 0x00008000    /* 32K */

    /* Space allocated for both code and variables in order to use the memory
    more efficiently.*/
    internal_ram:       org = 0x40008000,   len = 0x00028000 /* 160K */
    heap:               org = 0x40030000,   len = 0x00008000 /* 32K Heap */
    stack:              org = 0x40038000,   len = 0x00008000 /* 32K Stack */
}

SECTIONS
{
	/* z4 IVORxx and INTC branch tables */
    GROUP : {
    	/* Special section for INTC branch table required in hardware mode.
    	Place the .intc_hw_branch_table_p0 section first in order to used both core and INTC
    	tables. The intc_hw_branch_table should contain entries aligned to 16 bytes.
    	 */
        .intc_hw_branch_table_p0  ALIGN (0x10) : {}
        
        /* Because the Z4 IVORx are settable the IVOR branch table can be placed
        after the INTC HW table.*/
        .ivor_branch_table_p0 (VLECODE) ALIGN (0x10) : {}
        
        /* ISR handlers code. */
        .__exception_handlers_p0  (VLECODE) : {}
                
    } > exception_handlers_p0

    GROUP : {
        /* Section used for initialization code: __ppc_eabi_init.c,
        MPC56xx_HWInit.c, MPC56xx_init_*.c and the entry point (__startup).
        */
        .init : {}
        .init_vle (VLECODE) : {
            *(.init)
            *(.init_vle)
        }

        .text (TEXT) : {}
        .text_vle (VLECODE) : {
             *(.text)
             *(.text_vle)
         }

        .rodata (CONST) : {
            *(.rdata)
            *(.rodata)
        }

        .ctors : {}
        .dtors : {}
        extab : {}
        extabindex : {}
    } > internal_ram

    GROUP : {
    	/* Used in INTC SW mode to store the interrupt handlers array. Should be aligned to 4K. */
       .__uninitialized_intc_handlertable ALIGN(0x1000) : {}
       .data   : {}
       .sdata  : {}
       .sbss   : {}
       .sdata2 : {}
       .sbss2  : {}
       .bss    : {}
    } > internal_ram

}
/* Freescale CodeWarrior compiler address designations */
_stack_addr = ADDR(stack)+SIZEOF(stack);
_stack_end  = ADDR(stack);
_heap_addr  = ADDR(heap);
_heap_end   = ADDR(heap)+SIZEOF(heap);

/* If INTC HW mode is used it represents the vector base address to set
IVPR and the location of intc_hw_branch_table_p0 section. The EXCEPTION_HANDLERS
will point to the IVOR branch table.
*/
__IVPR_VALUE = ADDR(exception_handlers_p0);

/* IVOR branch table location. Used in Exceptions.c */
EXCEPTION_HANDLERS = ADDR(.ivor_branch_table_p0);