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@@ -14,7 +14,7 @@
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\title{A high-throughput readout architecture based on PCI-Express Gen3 and DirectGMA technology}
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-\author{M.~Vogelgesang$^a$, % HAHAHA ... let's wait for Michele to change that
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+\author{M.~Vogelgesang$^a$,
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L.~Rota$^a$,
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N.~Zilio,
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M.~Caselle$^a$,
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@@ -218,8 +218,6 @@ develop custom applications written in C or high-level languages such as Python.
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\section{Results}
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-% LR: The first sentence is more than obvious, and "experiment", woah!
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-% MV: You are an idiot. But sorry, I again stated the obvious.
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We carried out performance measurements on a machine with an Intel Xeon E5-1630
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at 3.7 GHz, Intel C612 chipset running openSUSE 13.1 with Linux 3.11.10. The
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Xilinx VC709 evaluation board was plugged into one of the PCIe 3.0 x8 slots.
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@@ -321,23 +319,6 @@ non-Gaussian distribution with two distinct peaks indicates a systemic influence
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that we cannot control and is most likely caused by the non-deterministic
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run-time behaviour of the operating system scheduler.
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-%% Here: instead of this useless plot, we can plot the latency vs different data
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-%% sizes transmitted (from FPGA). It should reach 50% less for large data
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-%% transfers, even with our current limitation... Maybe we can also try on a normal
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-%% desktop?
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-
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-
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-% \begin{figure}
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-% \centering
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-% \includegraphics[width=0.6\textwidth]{figures/latency}
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-% \caption{%
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-% For data transfers larger than XX MB, latency is decreased by XXX percent with respect to the traditional approach (a) by using our implementation (b).
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-% }
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-% \label{fig:latency}
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-% \end{figure}
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-
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-% In case everything is fine.
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-
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%% EMERGENCY TEXT if we don't manage to fix the latency problem
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% The round-trip time of a memory read request issued from the CPU to the FPGA is
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% less then 1 $\mu$s. Therefore, the current performance bottleneck lies in the
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