Reference Nieto paper

literature.bib

@@ -1,3 +1,16 @@
+@article{nieto2015high,
+  author = {J. Nieto and G. de Arcas and M. Ruiz and R. Castro and J. Vega and P. Guillen},
+  title = {A high throughput data acquisition and processing model for applications based on GPUs},
+  journal = {Fusion Engineering and Design },
+  volume = {96–97},
+  pages = {895--898},
+  year = {2015},
+  note = {Proceedings of the 28th Symposium On Fusion Technology (SOFT-28) },
+  issn = {0920-3796},
+  doi = {http://dx.doi.org/10.1016/j.fusengdes.2015.04.032},
+  url = {http://www.sciencedirect.com/science/article/pii/S0920379615002616},
+}
+
 @article{lonardo2015nanet,
   author = {A. Lonardo and F. Ameli and R. Ammendola and A. Biagioni and A. Cotta Ramusino and M. Fiorini and O. Frezza and G. Lamanna and F. Lo
       Cicero and M. Martinelli and I. Neri and P.S. Paolucci and E. Pastorelli and L. Pontisso and D. Rossetti and F. Simeone and F.
@@ -11,8 +24,6 @@
   year = {2015},
 }
 
-
-    
 @article{atlas_gpu,
   author={D Emeliyanov and J Howard},
   title={GPU-Based Tracking Algorithms for the ATLAS High-Level Trigger},
@@ -23,40 +34,39 @@
   url={http://stacks.iop.org/1742-6596/396/i=1/a=012018},
   year={2012},
 }
- 
+
 @inproceedings{panda_gpu,
-      author         = "Herten, Andreas",
-      title          = "{GPU-based Online Tracking for the PANDA Experiment}",
-      booktitle      = "{Proceedings, GPU Computing in High-Energy Physics
-                        (GPUHEP2014)}",
-      year           = "2015",
-      url            = "http://inspirehep.net/record/1386622/files/11.pdf",
-      pages          = "57-63",
-      doi            = "10.3204/DESY-PROC-2014-05/11",
-      SLACcitation   = "%%CITATION = INSPIRE-1386622;%%"
+  author         = {Herten, Andreas},
+  title          = {{GPU-based Online Tracking for the PANDA Experiment}},
+  booktitle      = {{Proceedings, GPU Computing in High-Energy Physics (GPUHEP2014)}},
+  year           = {2015},
+  url            = {http://inspirehep.net/record/1386622/files/11.pdf},
+  pages          = {57--63},
+  doi            = {10.3204/DESY-PROC-2014-05/11},
 }
 
+@article{alice_gpu,
+  author={Gorbunov, S. and Rohr, D. and Aamodt, K. and Alt, T. and Appelshauser, H. and Arend, A. and Bach, M. and Becker, B. and Bottger, S. and Breitner, T. and Busching, H. and Chattopadhyay, S. and Cleymans, J. and Cicalo, C. and Das, I. and Djuvsland, O. and Engel, H. and Erdal, H.A. and Fearick, R. and Haaland, O.S. and Hille, P.T. and Kalcher, S. and Kanaki, K. and Kebschull, U.W. and Kisel, I. and Kretz, M. and Lara, C. and Lindal, S. and Lindenstruth, V. and Masoodi, A.A. and Ovrebekk, G. and Panse, R. and Peschek, J. and Ploskon, M. and Pocheptsov, T. and Ram, D. and Rascanu, T. and Richter, M. and Rohrich, D. and Ronchetti, F. and Skaali, B. and Smorholm, O. and Stokkevag, C. and Steinbeck, T.M. and Szostak, A. and Thader, J. and Tveter, T. and Ullaland, K. and Vilakazi, Z. and Weis, R. and Zhongbao Yin and Zelnicek, P.},
+  journal={Nuclear Science, IEEE Transactions on},
+  title={ALICE HLT High Speed Tracking on GPU},
+  year={2011},
+  volume={58},
+  number={4},
+  pages={1845--1851},
+  ISSN={0018-9499},
+  month={8},
+}
 
-@ARTICLE{alice_gpu, 
-author={Gorbunov, S. and Rohr, D. and Aamodt, K. and Alt, T. and Appelshauser, H. and Arend, A. and Bach, M. and Becker, B. and Bottger, S. and Breitner, T. and Busching, H. and Chattopadhyay, S. and Cleymans, J. and Cicalo, C. and Das, I. and Djuvsland, O. and Engel, H. and Erdal, H.A. and Fearick, R. and Haaland, O.S. and Hille, P.T. and Kalcher, S. and Kanaki, K. and Kebschull, U.W. and Kisel, I. and Kretz, M. and Lara, C. and Lindal, S. and Lindenstruth, V. and Masoodi, A.A. and Ovrebekk, G. and Panse, R. and Peschek, J. and Ploskon, M. and Pocheptsov, T. and Ram, D. and Rascanu, T. and Richter, M. and Rohrich, D. and Ronchetti, F. and Skaali, B. and Smorholm, O. and Stokkevag, C. and Steinbeck, T.M. and Szostak, A. and Thader, J. and Tveter, T. and Ullaland, K. and Vilakazi, Z. and Weis, R. and Zhongbao Yin and Zelnicek, P.}, 
-journal={Nuclear Science, IEEE Transactions on}, 
-title={ALICE HLT High Speed Tracking on GPU}, 
-year={2011}, 
-volume={58}, 
-number={4}, 
-pages={1845-1851}, 
-ISSN={0018-9499}, 
-month={Aug},}
+@inproceedings{optical_pcie,
+  author={Liboiron-Ladouceur, O. and Wang, H. and Bergman, K.},
+  booktitle={Optical Fiber Communication and the National Fiber Optic Engineers Conference, 2007. OFC/NFOEC 2007. Conference on},
+  title={An All-Optical PCI-Express Network Interface for Optical Packet Switched Networks},
+  year={2007},
+  pages={1--3},
+  doi={10.1109/OFC.2007.4348447},
+  month={3},
+}
 
-@INPROCEEDINGS{optical_pcie, 
-author={Liboiron-Ladouceur, O. and Wang, H. and Bergman, K.}, 
-booktitle={Optical Fiber Communication and the National Fiber Optic Engineers Conference, 2007. OFC/NFOEC 2007. Conference on}, 
-title={An All-Optical PCI-Express Network Interface for Optical Packet Switched Networks}, 
-year={2007}, 
-pages={1-3}, 
-doi={10.1109/OFC.2007.4348447}, 
-month={March},}
-    
 @article{mu3e_gpu,
   author={S Bachmann and N Berger and A Blondel and S Bravar and A Buniatyan and G Dissertori and P Eckert and P Fischer and C Grab and R Gredig and M
 Hildebrandt and P -R Kettle and M Kiehn and A Papa and I Peric and M Pohl and S Ritt and P Robmann and A Schöning and H -C
@@ -69,11 +79,10 @@ Schultz-Coulon and W Shen and S Shresta and A Stoykov and U Straumann and R Wall
   url={http://stacks.iop.org/1748-0221/9/i=01/a=C01011},
   year={2014},
 }
-  
 
 @manual{xilinxgen3,
   title        = {Virtex-7 FPGA Gen3 Integrated Block for PCI Express},
-  author       = {Xilinx}, 
+  author       = {Xilinx},
   organization = {Inc. Xilinx},
   address      = {2100 Logic Drive, San Jose, CA 95124-3400},
   edition      = 4,
@@ -90,18 +99,18 @@ Schultz-Coulon and W Shen and S Shresta and A Stoykov and U Straumann and R Wall
   year = {2012},
   pages = {824--829},
   doi = {10.1109/HPCC.2012.116},
-  month = {June},
+  month = {6},
 }
 
-@ARTICLE{rota2015dma, 
-author={Rota, L. and Caselle, M. and Chilingaryan, S. and Kopmann, A. and Weber, M.}, 
-journal={Nuclear Science, IEEE Transactions on}, 
-title={A PCIe DMA Architecture for Multi-Gigabyte Per Second Data Transmission}, 
-year={2015}, 
-volume={62}, 
-number={3}, 
-pages={972-976}, 
-keywords={Linux;data acquisition;data communication;field programmable gate arrays;file organisation;ANKA synchrotron light source;FPGA design package;FPGA resources utilization;Linux driver;PCIe DMA architecture;Xilinx PCI Express;direct memory access;multiengine architecture;multigigabyte per second data transmission;Data communication;Engines;Field programmable gate arrays;Linux;Payloads;Registers;Throughput;Data Acquisition;FPGA;PCI express;direct memory access;high data throughput;high speed data streaming applications;readout electronics}, 
-doi={10.1109/TNS.2015.2426877}, 
-ISSN={0018-9499}, 
-month={June},}
+@article{rota2015dma,
+  author={Rota, L. and Caselle, M. and Chilingaryan, S. and Kopmann, A. and Weber, M.},
+  journal={Nuclear Science, IEEE Transactions on},
+  title={A PCIe DMA Architecture for Multi-Gigabyte Per Second Data Transmission},
+  year={2015},
+  volume={62},
+  number={3},
+  pages={972--976},
+  doi={10.1109/TNS.2015.2426877},
+  ISSN={0018-9499},
+  month={6},
+}

paper.tex

@@ -91,8 +91,15 @@ radiation hardness, lower power consumption and higher density.
 Lonardo et~al.\ lifted this limitation with their NaNet design, an FPGA-based
 PCIe network interface card with NVIDIA's GPUDirect
 integration~\cite{lonardo2015nanet}. Due to its design, the bandwidth saturates
-at 120 MB/s for a 1472 byte large UDP datagram. Moreover, the system is based on
-a commercial PCIe engine. Other solutions achieve higher throughput based on
+at 120 MB/s for a 1472 byte large UDP datagram. 
+% Moreover, the system is based on a commercial PCIe engine.
+% (MV: who cares?)
+Nieto et~al.\ presented a system that moves data from an FPGA to a GPU using
+GPUDirect and a PXIexpress data link that makes use of four PCIe 1.0 links
+\cite{nieto2015high}.  Their system (as limited by the interconnect) achieves an
+average throughput of 870 MB/s with 1 KB block transfers.
+
+Other solutions achieve higher throughput based on
 Xilinx (CITE TWEPP DMA WURTT??) or Altera devices (CITENICHOLASPAPER TNS), but
 do not support direct FPGA-to-GPU communication.