Started HW section

literature.bib

@@ -11,6 +11,16 @@
   year = {2015},
 }
 
+@manual{xilinxgen3,
+  title        = {Virtex-7 FPGA Gen3 Integrated Block for PCI Express},
+  author       = {Xilinx}, 
+  organization = {Inc. Xilinx},
+  address      = {2100 Logic Drive, San Jose, CA 95124-3400},
+  edition      = 4,
+  month        = 7,
+  year         = 2015,
+}
+
 @inproceedings{vogelgesang2012ufo,
   author = {Vogelgesang, M. and Chilingaryan, S. and dos Santos Rolo, T. and Kopmann, A.},
   booktitle = {High Performance Computing and Communication 2012 IEEE 9th
@@ -22,3 +32,16 @@
   doi = {10.1109/HPCC.2012.116},
   month = {June},
 }
+
+@ARTICLE{rota2015dma, 
+author={Rota, L. and Caselle, M. and Chilingaryan, S. and Kopmann, A. and Weber, M.}, 
+journal={Nuclear Science, IEEE Transactions on}, 
+title={A PCIe DMA Architecture for Multi-Gigabyte Per Second Data Transmission}, 
+year={2015}, 
+volume={62}, 
+number={3}, 
+pages={972-976}, 
+keywords={Linux;data acquisition;data communication;field programmable gate arrays;file organisation;ANKA synchrotron light source;FPGA design package;FPGA resources utilization;Linux driver;PCIe DMA architecture;Xilinx PCI Express;direct memory access;multiengine architecture;multigigabyte per second data transmission;Data communication;Engines;Field programmable gate arrays;Linux;Payloads;Registers;Throughput;Data Acquisition;FPGA;PCI express;direct memory access;high data throughput;high speed data streaming applications;readout electronics}, 
+doi={10.1109/TNS.2015.2426877}, 
+ISSN={0018-9499}, 
+month={June},}

paper.tex

@@ -33,6 +33,24 @@
 Citation~\cite{lonardo2015nanet}
 
 
+\section{Hardware implementation}
+
+The architecture of the DMA engine described in \cite{rota2015dma} has been 
+extended to support the Xilinx PCI-Express Gen3 Core \cite{xilinxgen3}, with 
+some minor modifications:
+
+\begin{itemize}
+\item the RX and TX DMA engines does not share any logic with the Programmed 
+Input-Output (PIO) interface, thanks to novel connections implemented in the 
+Gen3 PCI-Express Core.
+\item the maximum page size associated with each descriptor is increased to 2 
+GBytes.
+\item the input stage has been increased to 256 bits operating
+at 250 MHz, resulting in a maximum throughput of 7.6 GBytes/s, which saturates
+the PCI-Express Gen3. 
+\end{itemize}
+
+
 \section{Architecture}
 
 \subsection{Host side}