Added support for setting Gain and Offset of more than 4 channels

KCG/base/backend/board/board_config.py

@@ -4,6 +4,7 @@ Configuration for each board
 
 import os
 import sys
+import traceback
 if sys.version_info[:3] < (3,0):
     import ConfigParser as configparser
 else:
@@ -466,6 +467,7 @@ class BoardConfiguration(QtGui.QWidget):
                     callback(value)
                 except Exception as e:
                     log.error('Observer Callback error: {}'.format(e))
+                    print(traceback.format_exc())
 
         for cb in self._observers_for_all:
             try:
@@ -482,6 +484,7 @@ class BoardConfiguration(QtGui.QWidget):
                         callback(value)
                     except Exception as e:
                         log.error('Observer Callback error: {}'.format(e))
+                        print(traceback.format_exc())
                     time.sleep(0.025)
 
     def _notify_observers(self, key, value, write=True):
@@ -647,39 +650,112 @@ class BoardConfiguration(QtGui.QWidget):
             logging.error("Error in Board Communication, was unable to write value to board "+reason)
 
     def _set_adc_gain(self, x):
-        self._select_adc(1)
+
+        #Bits 1 and 2 of register 9044 control which SPI channels to select.
+        #SPI_1 will route to  ADC-Element 1 (Channel 1 and 2), and SPI_2
+        #will route to ADC-Element 2 (Channel 3 and 4).
+
+        #Bits 16 and 17 of register 9044 control which FMCs to route the
+        #SPI commands to. If both bits are 1, then the SPI commands get routed
+        #to both FMCs at the same time.
+
+        #pci.read response is returned as a list. Since we expect only one
+        #value, we access index [0]
+        initial_mux_config = pci.read(self.identifier, reg='9044')[0]
+
+
+        #Select SPI1 and FMC1
+        updated_mux_config = initial_mux_config | 0x10002
+        pci.write(self.identifier, hex(updated_mux_config), '0x9044')
+
         pci.write(self.identifier, '46{:04x}'.format(int(x[0])), '0x9064')
         pci.write(self.identifier, '56{:04x}'.format(int(x[1])), '0x9064')
 
-        self._select_adc(3)
+
+        #Select SPI2 and FMC1
+        updated_mux_config = initial_mux_config | 0x10004
+        pci.write(self.identifier, hex(updated_mux_config), '0x9044')
+
         pci.write(self.identifier, '46{:04x}'.format(int(x[2])), '0x9064')
         pci.write(self.identifier, '56{:04x}'.format(int(x[3])), '0x9064')
 
-        if len(x) > 4:
-            logging.vinfo("Gain update not defined for more than 4 adc")
+
+        if len(x) > 4 and len(x) < 9:
+
+            #Select SPI1 and FMC2
+            updated_mux_config = initial_mux_config | 0x20002
+            pci.write(self.identifier, hex(updated_mux_config), '0x9044')
+
+            pci.write(self.identifier, '46{:04x}'.format(int(x[4])), '0x9064')
+            pci.write(self.identifier, '56{:04x}'.format(int(x[5])), '0x9064')
+
+
+            #Select SPI2 and FMC2
+            updated_mux_config = initial_mux_config | 0x20004
+            pci.write(self.identifier, hex(updated_mux_config), '0x9044')
+
+            pci.write(self.identifier, '46{:04x}'.format(int(x[6])), '0x9064')
+            pci.write(self.identifier, '56{:04x}'.format(int(x[7])), '0x9064')
+
+        else:
+            logging.vinfo("Gain update not defined for more than 8 adc")
+
+
+        #Restore the initial MUX Configuration
+        pci.write(self.identifier, hex(initial_mux_config), '0x9044')
+
 
     def _set_adc_offset(self, x):
-        #ADC1
-        self._select_adc(1)
+
+        #Bits 1 and 2 of register 9044 control which SPI channels to select.
+        #SPI_1 will route to  ADC-Element 1 (Channel 1 and 2), and SPI_2
+        #will route to ADC-Element 2 (Channel 3 and 4).
+
+        #Bits 16 and 17 of register 9044 control which FMCs to route the
+        #SPI commands to. If both bits are 1, then the SPI commands get routed
+        #to both FMCs at the same time.
+
+        #pci.read response is returned as a list. Since we expect only one
+        #value, we access index [0]
+        initial_mux_config = pci.read(self.identifier, reg='9044')[0]
+
+
+        #Select SPI1 and FMC1
+        updated_mux_config = initial_mux_config | 0x10002
+        pci.write(self.identifier, hex(updated_mux_config), '0x9044')
+
         pci.write(self.identifier, '44{:04x}'.format(int(x[0])), '0x9064')
         pci.write(self.identifier, '54{:04x}'.format(int(x[1])), '0x9064')
 
-        self._select_adc(3)
+
+        #Select SPI2 and FMC1
+        updated_mux_config = initial_mux_config | 0x10004
+        pci.write(self.identifier, hex(updated_mux_config), '0x9044')
+
         pci.write(self.identifier, '44{:04x}'.format(int(x[2])), '0x9064')
         pci.write(self.identifier, '54{:04x}'.format(int(x[3])), '0x9064')
 
-        if len(x) > 4:
-            logging.vinfo("Offset update not defined for more than 4 adc")
-
-    def _select_adc(self, nr):
-        val = 0
-        if nr == 0:
-            val = 0
-        if nr < 3:
-            val = 4
-        elif nr < 5:
-            val = 2
-        pci.write(self.identifier, hex(val), '0x9044')
+
+        if len(x) > 4 and len(x) < 9:
+
+            #Select SPI1 and FMC2
+            updated_mux_config = initial_mux_config | 0x20002
+            pci.write(self.identifier, hex(updated_mux_config), '0x9044')
+
+            pci.write(self.identifier, '44{:04x}'.format(int(x[4])), '0x9064')
+            pci.write(self.identifier, '54{:04x}'.format(int(x[5])), '0x9064')
+
+
+            #Select SPI2 and FMC2
+            updated_mux_config = initial_mux_config | 0x20004
+            pci.write(self.identifier, hex(updated_mux_config), '0x9044')
+
+            pci.write(self.identifier, '44{:04x}'.format(int(x[6])), '0x9064')
+            pci.write(self.identifier, '54{:04x}'.format(int(x[7])), '0x9064')
+
+        else:
+            logging.vinfo("Offset update not defined for more than 8 adc")
+
 
     def _set_samplingrate(self, rate):
         return